National Semiconductor Corp introduced a whole new RISC instruction set in an attempt to woo the embedded market. Project Piranha looks conceptually similar to Motorola’s ACE/ColdFire project – an attempt to combine the best of RISC and complex models to benefit the embedded market. Piranha is described as a common RISC architecture that can scale from 8-bit to 32-bit implementations. Its brief: to avoid RISC bloat – the relatively high amounts of memory that RISC requires to store its programs. Most manufacturers take general purpose chips and strip them for embedded applications, NatSemi is working from scratch – it says its core sizes will be significantly smaller than other RISC cores, will require less power and will eliminate the complexity of general-purpose RISC. On the code-size reduction front, it has taken the unusual step of allowing variable length instructions in a RISC architecture – the result, it says, is that the 32-bit implementation of Piranha has code densities similar to Motorola’s 68000 while the 16-bit version produces even tighter code. Variable length instructions do not sound particularly RISCy, but NatSemi says that they are designed with a format that makes them easy for the chip to decode and despatch. Piranha 16, built in 0.8 micron silicon, has a core size of just 3 square mm. The 32-bit implementation is 4.5 square mm – even smaller than the ARM-7 core. Performance is better than ARM-6 and 80386 at 25MHz, worse than the ARM-7. At 30MHz the 32-bit part does 43K Drhystones; the 16-bit can do 33K Drhystones.
