IBM Corp talked airily about having simply added a cache with controller and optimised the microcode to create its 20MH 386SLC version of Intel Corp’s 80386SX chip (CI No 1,783) but the company was hiding some fairly intense light under an exceedingly large and smothering bushel. The announcement material and presentations contained no mention of a string of interesting features in the IBM chip that will enable IBM to do a lot of clever things with it in future products. But the Sebastopol, California-based Microprocessor Report has taken the lid off and uncovered a string of IBM secrets. First up, the 386SLC is a redesign from the ground up, so that internally it is more like an 80486 design in an 80386SX pin-out, though IBM has taken a different design approach to Intel. In IBM’s design, explains the Californian publication, register-to-register operations take two cycles, compared with Intel’s one cycle. At the same time, however, IBM’s design is twice as fast as Intel’s 80486 in terms of memory-to-register operations – these take two clock cycles; Intel takes four. And IBM’s device also speeds up high-clock-count instructions – string moves, call, loop and protected mode functions and the like – which aren’t addressed by the Intel 80486. Some of those instructions, according to IBM, often appear in personal computer software. IBM, of course, has had the privilege of access to Intel’s 80386 design database, something denied to other manufacturers producing Intel-compatible products. IBM is also fortunate enough to be in possession of a licence to produce its own 80386-architecture processors. As with Intel’s 80486, the SLC’s on-chip cache is integrated into the CPU pipeline to provide single-cycle access, and is effectively two clock cycles faster than the fastest possible 80386SX external cache. Features of the new IBM chip that aren’t used in its first application, the PS/2 Model 57, include a new interrupt level to support a power-management mode similar to those implemented by Intel itself and by Chips & Technologies Inc. This is achieved by the use of five of the 80386SX’s 11 no-connect pins. Several pins are also used for cache support, similar to Chips & Technologies’ 38605, the newsletter reveals. Many of the new functions also can be controlled by software. For example, new registers can enable or disable the address bit 20 mask function under software control, and non-cacheable regions can be specified with the implementation of a set of registers. As previously reported, IBM reckons its 386SLC is 88% faster than an Intel 80386SX using Lotus Development Corp’s 1-2-3 spreadsheet package as a benchmark; 84% faster on Excel for OS/2; and 56% faster on Word for Windows. On Dhrystones, the 20MHz IBM part is claimed to rate 10,000, against Intel’s 3,900, but Dhrystone does exaggerate the benefit of the small cache; IBM concludes that its SLC is faster than a 16MHz Intel 80486SX. Although the PS/2 Model 57 upgrade ties both clock signals together, the 386SLC provides separate, asynchronous clock inputs for the bus interface and the processor core. The processor core could be clocked at twice the speed of the bus, as in Intel’s forthcoming clock-doubler 80486 processors (CI No 1,785), but the two clocks aren’t limited to any fixed – or even integral – relationship. A future upgrade card could provide a bigger performance boost by having its own clock oscillator – or clock multiplier – to run the CPU core at a faster rate than the rest of the system. The SLC is fabricated in IBM’s 0.8 micron, three-level-metal CMOS process, and integrates 875,000 transistors and the package includes a metal slug to improve heat dissipation. IBM says it has no plans to sell the device as a chip-level product presumably this is a restriction imposed by Intel rather than a strategic decision by IBM. IBM’s contract with Intel limits IBM to producing an undisclosed percentage of its 80386 needs, which may limit IBM’s ability to switch the mainstream of its product line to its own microprocessors.
