A NAND joint-venture between Toshiba and SanDisk has resulted in the creation of a 48 layer second generation 3D NAND, dubbed Bit Cost Scaling (BiCS).
The chipmaker used traditional floating gate design for the creation of BiCS, and also used insulating material to create a charge trap to reduce electron leakage.
Toshiba previously developed, what they claim, is the smallest planar NAND node (15nm).
Toshiba reportedly said that 3D NAND would exist in parallel for some time, which hints that the manufacturing of 48 layers 3D NAND could have cost the company more to manufacture than the 15nm planar NAND, reported AnandTech.
SanDisk memory technology EVP, Dr. Siva Sivaram, said: "We are very pleased to announce our second generation 3D NAND, which is a 48 layer architecture developed with our partner Toshiba.
"We utilised our first generation 3D NAND technology as a learning vehicle, enabling us to develop our commercial second generation 3D NAND, which we believe will deliver compelling storage solutions for our customers."
According to SanDisk, pilot production will begin in the second half of 2015 in the Yokkaichi joint venture facility, with commercial production expected to start in 2016.
