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May 25, 2016

IBM, Qualcomm, ARM join forces to standardise data centre interconnects

News: Consortium aims to end 'one size fits all architecture' in the hosting arena.

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A group of seven global data centre giants have come together to develop a single interconnect technology specification to allow processers using different instruction set architectures (ISA) to share data with accelerators in the data centre.

AMD, ARM, Huawei, IBM, Mellanox, Qualcomm and Xilinx have founded the Cache Coherent Interconnect for Accelerators Consortium (CCIX) to drive a high-performance open acceleration framework into the hosting industry, which will see different vendors’ CPUs and accelerators communicate with each others while sharing the same memory.

As data centres come under pressure to accelerate applications processing due to power and space constraints, applications such as big data analytics, search, machine learning, NFV, wireless 4G and/or 5G, in-memory database processing, video analytics, and network processing, benefit from acceleration engines that need to move data seamlessly among the various system components.

The CCIX aims to let different data centre processors work together and process data without taking into account where the processor resides. This will turn processors in the data centre location-agnostic.

The organisation will leverage existing server interconnect infrastructure and deliver higher bandwidth, lower latency, and cache coherent access to shared memory

The consortium also expects the move to dramatically reduce the need for complex programming environments.

As a result, performance and usability should be improved by enabling a driver-less and interrupt-less usage model.

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According to the consortium, additional capabilities include both off-load and bump-in-the-wire inline application acceleration while leveraging existing server ecosystems and form factors thereby improving total cost of ownership (TCO), and higher bandwidth compared to the existing interface.

Furthermore, application latency is also expected to be significantly improved as interoperability cuts down processing times, and lastly, seamless processors and accelerators hardware cache on coherency support.

Lakshmi Mandyam, director server systems and ecosystems, ARM, said: "A ‘one size fits all architecture‘ approach to data centre workloads does not deliver the required performance and efficiency.

"CCIX enables more optimised solutions by simplifying software development and deployment of applications that benefit from specialised processing and hardware off-load, delivering higher performance and value to data centre customers."

Gilad Shainer, vice president of Marketing at Mellanox, said that the CCIX enables greater performance and connectivity capabilities over existing interconnects, and "actually paves the road to the next generation CPU – Accelerator – Network standard interface".

He said: "With an anticipated broad eco-system support of the CCIX standard, data centres will now be able to optimise their data usage, thereby achieving world-leading applications efficiency and scale."

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