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June 11, 2019

Why Intel Wants a PISA Barefoot Networks

Program top-of-rack switches to spread traffic, find faults...

By CBR Staff Writer

Silicon is, naturally, hugely important in the data centre as workloads grow ever-more demanding. But as more and more data flows through hyperscale data centres, so are interconnects, and network intelligence: these are crucial for numerous reasons, not least because a network outage can cost an investment bank user – by way of one example – millions per minute; yet current tools to identify network issues still often boil down to ping and traceroute: connectivity tools created over 20 years ago.

Despite this, the networks that are interconnecting servers in hyperscale data centres are typically built using fixed-function Ethernet switches: rapid but not programmable hardware, which does not allow teams to improve the way packets are processed in their networks. The reason: programmable switches are typically slow and in a world in which speed is everything, the trade-off in terms of flexibility not been there.

Intel’s acquisition this week of Barefoot Networks, a Palo Alto-based network hardware startup, puts the focus firmly on the growing importance of interconnects, and the flurry of innovation that has put them centre stage as legacy network hardware increasingly becomes an obstacle to progress at the hyperscale level. (Think of fixed function switches as the relational databases of the data centre world: entrenched, powerful, but increasingly inflexible, stifling innovation and requiring workarounds…)

See also: Intel Open Sources a Kubernetes-Native Deep Learning Platform

The deal follows hot on the heels of Nvidia’s acquisition of Israel’s Mellanox, another networking hardware specialist, for $6.9 billion in March. And what it really points to is the rapidly emerging need for network telemetry and intelligence at the data centre level itself. (Barefoot Networks has described itself in the past as “to the networking industry what Nvidia is to the graphics industry: like us, their primary interaction with customers is in software. But their revenue is mostly from chips.”)

Intel described the acquisition as giving it “deep expertise in cloud network architectures, P4-programmable high-speed data paths, switch silicon development, P4 compilers, driver software, network telemetry and computational networking” Intel said. (P4 is a programming language designed for programming of network switches).

Here’s what that means…

What Barefoot Networks Does, and Why Intel Wants It

Barefoot is the creator of PISA (Protocol Independent Switch Architecture), a way of letting users can program a network for themselves, without any degradation in performance, using the open-source programming language P4. (A language co-developed alongside

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Programmable network systems, the company believes, will lead to a “Cambrian explosion of innovation” in networking as data centre networks start to evolve alongside the applications running on their servers, rather than being stuck in the “Dark Ages” of fixed function switches.

A typical example of the kind of data centre improvement it sees is the disaggregation of middleware bloat typical to many data centres.

Barefoot offers the example of a large data centre operator that currently uses a complex Network Function Virtualisation (NFV) cluster of thousands of servers to load-balance incoming packets across web servers. “By programming the top-of-rack switches [instead] to spread traffic, keeping track of which servers are up and running, they plan to repurpose thousands of servers to run revenue-generating applications instead.”

Recovering from Outages

Critically, a programmable forwarding plane, where users can quickly deploy tests and probes, can reduce the time to recover from an outage, Barefoot Networks notes in one whitepaper.

“In one interesting example, packets were being dropped due to congestion in a switch once every minute. The intermittency of the failure made it hard to pin-point which application and cross-traffic was causing the problem. In a fixed switch environment debugging this problem is nearly impossible. However, using programmable switches, a programmer added a feature to their switch that inserts the current occupancy of the packet buffers to every passing packet, immediately identifying the rogue application clogging the network.”

The PISA architecture, in short, does for networking what the DSP did for signal processing, the GPU did for graphics and the TPU is doing for machine learning, Barefoot claims. “It is putting full control in the hands of the network owner.” That control is a powerful thing. And now it belongs to Intel, along with Barefoot’s “Tofino” high speed programmable switch silicon and “Capilano”, the compilers and development tools needed to compile and debug programs to run on Tofino.

With Intel looking to move to more flexibility in architectures, heavily pushing its FGPAs and pushing out an increasing number of open source tools, the fit looks good. The price (terms were not disclosed) for Barefoot’s’ wizardry looks like it will remain a closely guarded secret.

Read this: Intel Unveils New Architectures: Open API, 3D Stacking, More


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