Cypress Semiconductor Corp has released a multi-processing cache controller and memory management unit, the CY7C605, for building systems with up to four Sparc processors: it complies with level 2 of the MBus multi-processing specification for Sparc-based architectures and is available in 25MHz, 33MHz and 40MHz implementations; it’s out in August and prices go from $1,200 each for the 40MHz version in quantities of 100-up.
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