The VMEbus International Trade Association, a consortium of over 150 firms – which includes most of the Unix-based workstation and minicomputer community – has given its backing to the newly drafted Futurebus+ specification in a move likely to make it the standard bus architecture for future generations of systems (CI No 1,364). Futurebus+ should eventually lead to the creation of exceptionally powerful computers – up to 100 times faster than today’s VMEbus machines – for industry and business, by replacing custom designs used in most computers so that they will cost far less, yet be able to do much more work – that’s the theory anyway.

No fees or licences

The VMEbus Association has already developed a bridge specification to Futurebus+ for the VMEbus, and a group of manufacturers including Intel are understood to have a similar bridge for the Multibus II. As there are no fees or licences attached, the bridges will mean that 680X0 and 80X86 developers could implement the Futurebus+ specification in board and system designs, overcoming the perennial problem of proprietary bus compatibility that has dogged the industry for years. All that is now left wanting is the bus silicon itself – cache, protocol, interface, message passer and command interpreter chips. Companies currently doing the work are thought to include National Semiconductor, Signetics and Plessey, as well as Hughes Aircraft which is understood to have a prototype bridge board already in place. With the enormous possibilities that the Futurebus+ brings, the RISC chip manufacturers are now queuing up to bring their designs into line. Norsk Data’s Dolphin subsidiary says Futurebus+ will be an integral part of its 1,000 MIPS, ECL Motorola 88000 processor – thought to be close to the beta testing stage in Europe – Intergraph has been working hard to get the Clipper into Futurebus+ shape and others are working on the Sparc and MIPS chips. In addition DEC’s research is thought to be particularly advanced, indeed Futurebus+ could appear in the next VAXes. Unix will be the first operating system to run with Futurebus+-based systems, likely to be followed by Apple’s MacOS. The Futurebus+ began life back in the 1970s as an IEEE project to develop specifications for a high performance non-proprietary bus architecture. By 1978 the IEEE P896 committee was working on the task, and an initial 32-bit specification drafted, now superseded by a fully-scalable design that can handle word-lengths of up to 256 bits. After many years in technological backwaters, support for Futurebus+ really took off last year when the US Navy announced that the bus would be a mandatory requirement for its computer purchases after 1991. With the lure of millions of dollars worth of business – it is reckoned the total Futurebus+ market will be worth $50,000m-up by 2000 – this carrot has drawn the major manufacturers towards Futurebus+ and pushed it to centre stage via their participation in the VMEbus Association. Member companies include DEC, Sun Microsystems, National Semiconductor, Motorola, Unisys, and the Spirit Consortium. –

By William Fellows

First Futurebus+ backplane boards are expected by the end of this year, with full systems emerging onto the market over the next couple of years. Futurebus+ has wide-ranging implications for the expansion of distributed computing and fault-tolerant solutions, global memory architecture and improved cache memory. Technological developments that have made the Futurebus possible are a new backplane medium devised by National Semiconductor known as Backplane Tranceiver Logic, the Metral 2mm high signal line density connector system unveiled by AT&T and Du Pont in October of last year, together with vastly improved handshaking techniques. The specification can use a 256-bit wide word delivered through parallel single bit pathways. Each of these pathways is expected to switch via silicon components at around 25nS, delivering 40m to 60m transfers of these 256-bit words each second. That’s equivalent to a serial throughput of 12Gb per second. The first imp

lementations are expected to use 64-bit wide datapaths, making them about a quarter of that speed, but once Gallium Arsenide components are introduced – towards the end of next year – then the full 256-bit systems will yield a full 25.6Gbps transfers, faster than the internal bus speeds on modern mainframes. Whilst all this sounds impressive, it may be up to three years before Futurebus+ becomes competitive with existing VME systems in terms of price-performance because of the need to produce new gate arrays and the like, but it is much needed as these existing bus structure are being outstripped by the power and speed of even current generation processor technology. However Bob Squirrel of GMT Ltd, Leatherhead, Surrey, who has been at the forefront Futurebus+ research in the UK says that whilst he believes that industry implications of Futurebus+ are mind-boggling, it will be the last of the backplane buses by virtue of the fact that it pushes the physical possibilities of backplane technology to the limits. Indeed a future generation bus technology is already under development, known as the SCI Scalable Coherent Interface – bus, a ring connection actually built into the system rather than a backplane as such – Norsk Data is already working on just such a bus – the good news is that Futurebus+ has been designed to integrate with it.

Spirit workstation

The European Spirit consortium is backing Futurebus+, and the first Spirit workstation is due to be released at the beginning of next year, according to technical co-ordinator Martin De Lange, who is also managing director of Dutch software house Associated Computer Experts BV, Amsterdam. Based on an implementation of the Futurebus+ – though the silicon source for the bus is not disclosed – and initially using the Motorola 68040, the Spirit is rated at 50 MIPS running ACE’s multi-processing implementation of AT&T Unix. Queen Mary College, London, is designing a three-dimensional graphical user interface for the Spirit, which should be ready in the second half of the year. As other Futurebus+-compliant chip designs begin to emerge it should mean that Spirit is freed from the constraints of one particular processor architecture. The consortium developing Spirit – which includes British Aerospace, Kontron Elektronik GmbH, ACE, Caption SA of Rennes, University of Tunigen, University of Sussex and QMC – expects that RISC chips such as the Motorola 88000 and Sun Microsystems’ Sparc will become available for use in the workstation. A second, 1,000 MIPS version of the Spirit will be launched by the end of 1992. It will include extensive parallel features and may run Paris-based Chorus Systemes’ as yet unreleased distributed, multi-processing multi-threaded Unix, a kind of European version of Carnegie-Mellon’s Mach Unix implementation.