Groupe Bull and SGS-Thomson Microelectronics NV say they have demonstrated the utility of a 0.5-micron CMOS process technology for a 5m-transistor complex instruction set processor that was developed within the Joint European Submicron Silicon project. The companies said the 32-bit processor found in Bull’s DPS 7000 mainframes was sucessfully converted to the HCMOS5 technology for use in the company’s first pass at a parallel mainframe, and was developed by SGS-Thomson and its partners France Telecom, CNET, Centre Nationale des Etudes Telecommunications and Philips Electronics NV. Layout tapes for the processor were submitted to SGS-Thomson in May and Bull says it received the first silicon samples two months later from the factory at Crolles, France. The processor integrates the complete central processor unit and first-level cache, 64Kb representing 3.4m transistors, on a 225-square-millimeter silicon area. According to the two companies, the JESSI HCMOS5 process demonstrated some unique capabilities: probe yields that were between two and 10 times higher than those observed on similar processes from US or Japanese manufacturers; performance measured on ring oscillators that showed an improved intrinsic speed; and good integration of static RAM with logic, since approximately 90% of the good dies demonstrated that the 64Kb embedded on the chip were 100% functional.
