Also unveiled at the Supercomputing show was the experimental 200Mflops CHoPP 1 from CHoPP Computer Corp of La Jolla, California. Described as faster than a Cray X/MP, the version shown in Santa Clara had only a single node, but the company plans production models to have between four and 16 nodes, each with 64 sets of 128 registers to hold a complete CPU state of 64 tasks, and data for as many as 2,048 jobs. A hardware task manager handles all queueing and scheduling of tasks without software intervention to achieve highly parallel performance. Physically, reports Microbytes Daily, the air-cooled processor consists of a stack of up to 19 horizontally laid 24 by 24 circuit boards sandwiched and held in place by five bolts that protrude from the top, squeezing the boards together so connections are made at more than 150,000 wireless board-to-board interconnect points, eliminating backplane wiring and greatly reducing path lengths for a 20% performance boost. The machine executes nine instructions per clock cycle – one every 6.7nS; effective throughput is claimed at 200 Mflops. The base machine, set for mid-1988, will go for $4m, a 16-node system for $25m.
CHOPP SHOWS OFF ITS EXPERIMENTAL PARALLEL CHOPP 1
