The agreement was reached in an effort to promote the standardization of wafer level package (WLP) technology, and marks the first time Casio has made it available to another Japanese semiconductor device manufacturer.
Terms of the partnership include the continuing utilization of Casio’s WLP technology by Renesas Technology in the fabrication of its semiconductor devices, and the authorization of Renesas Technology to manufacture and sell chip size package (CSP)(a)(1) products employing WLP, both on its own and through its subsidiaries.
WLP aims to enable rerouting of the copper traces and encapsulation of chips in epoxy resin while the wafer is intact. It is hoped that it will allow Renesas Technology to further meet the requirements of its customers and the increasing demand for compact electronic products by offering a broader array of package options.
Both Casio and Renesas Technology anticipate that the present agreement will lead to an even stronger relationship between the two companies in future.
