Electronic design automation company, Cadence Design Systems Inc has unveiled a chip layout design system which it claims will cut IC design times compared with traditional methods. The system, called automated custom psychical design (ACPD), is made up of a bundle of the firm’s circuit design tools – including its Virtuoso XL layout editor and Virtuoso custom router. The software allows graphical representation of the back-end stage of chip design, laying out and manipulating objects on an image of the circuit. San Jose, California-based Cadence claim that while the number of transistors on a die has risen drastically, designers haven’t kept pace, often drawing circuits. According to firm, this causes a bottleneck in the design process and claims that its system will reduce design times for ICs by 5% to 10%.
