AT&T Information Systems and Bell Laboratories are working on a 32-bit Reduced Instruction Set microprocessor that they call Crisp, for C language Reduced Instruction Set Processor. The part, which has been designed in 1.75 micron CMOS with three levels of interconnect, integrates 172,163 transistors – but 100,000 of them are for the 13K of cache memory. The part has no registers as such, but sets up 32 internal stack cache registers. It has a mere 35 basic instructions and the arithmetic logic unit is made up of two elements, each of which executes a three-stage pipeline. They are the pre-fetch decode unit and the execution unit. The Crisp also includes seven static memory arrays and two programmable logic arrays, one for macros, the other for the multi-cycle functions such as multiply. The part was described at the International Solid State Circuits Conference, and will no doubt turn up in future AT&T Information Systems products.
Content from our partners
