Bloodied it may be in the computer and semiconductor businesses, but AT&T Co is by no means bowed, as its two new challenges in the digital signal processing arena make clear (CI Nos 734, 735). New ways of manipulating images with a computer at previously unimagined speeds are flooding out of US start-ups and established companies alike, but even against the host of rival offerings, the new AT&T PXM 900 image display system looks to be something pretty special. AT&T certainly thinks so – the product gets its own brand new business division, AT&T Pixel Machines. AT&T is aiming the PXM 900 Series – designed to be front-ended by a Sun Microsystems workstation – at applications that require real time display of complex objects, such as the rendering and animation of three-dimensional objects, visual simulation, image processing, and volume data display and analysis. According to the new division it has used all Bell Laboratories’ skills and expertise in parallel processing architectures, graphic research and digital signal processing to come up with the product. AT&T explains that digital signal processors are integrated circuits that process very high volumes of data by multiplying numbers at blazing speeds and with great accuracy – shouldn’t that be precision?
Five or six Cray 1s
Target customers for the Pixel Machine include scientific and research end users, value-added resellers and system integrators. On the software front, AT&T is a bit vague, but a graphics library and diagnostics are standard with each system and software tools including a C compiler, linker and assembler are promised. AT&T is particularly proud of the optimising C compiler, which it reckons is a definite first, and will lead to much wider application of signal processors – it will also be available on the company’s latest DPS32 variant – because it will make the things so much easier to program. On the hardware front, the PXM 900 has a complex and ingenious architecture to push through and keep track of all those fragmentary picture images. It uses a parallel architecture with a large, tightly coupled image memory. Up to 82 floating point processors are used to provide around 800 MFlops of peak performance when they are all able to work together – that in theory means something like five or six Cray 1s all sorting out the details of your picture – right behind the screen on your desktop. Each PXM 900 consists of four functional units: a high-speed parallel interface, a Transformation Pipeline, a parallel array of Pixel Nodes and a video controller, configured on a familiar old standard VME bus. The Transformation Pipeline consists of nine processors called Transformation Nodes which perform transformations, clipping and other geometric operations on incoming data. The resulting data is then sent to the Pixel Nodes over a 32-bit broadcast bus – and an optional second pipeline can be added to increase performance. The Pixel Nodes, which are configured in parallel, perform all the rendering and rasterising, with each node operating independently and simultaneously on a portion of a distributed frame buffer.
Snow White & Dwarfs
AT&T says that this division of the frame buffer is unique to the PXM, and is and achieved through a pixel interleaving scheme which results in a balanced load on each node and uniform rendering time on the screen. The PXM 900 can be configured with 16, 20, 32, 40 or 64 Pixel Nodes. The output from the Pixel Nodes is passed to the Pixel Funnel which multiplexes the data and in turn squirts it out onto a high resolution monitor. Each of the processors in the PXM 900 series is an AT&T DSP32 floating point processor – that’s up to 82 separate DSP32 processors – and is fully programmable, which, Pixel Machines says, enables the PXM 900 to be tailored to fit individual user needs as well as to take advantage of new developments in graphics and image processing algorithms. The initial series of five products in the PXM 900 series is modular: any configuration can be upgraded without affecting the compatibility of existing sof
tware, and for those with very large image processing workloads, prices look very keen, ranging from $44,500 to $119,500. The Pixel Machine uses the existing NMOS version of the DSP32, but if you want to get an animator really animated, just give him an idea of what he’ll be able to do when AT&T gets around to putting its second generation version of the chip into the Pixel Machine architecture – create the entire visual footage of Disney’s Snow White & the Seven Dwarfs in a month – but with much greater detail? Confusingly, AT&T announced the two developments, quite separately, in the same week, the linking factor being the optimising C compiler. The second generation chip should find its way into the Pixel Machine quite soon, because it is due out in the second quarter of 1988, from AT&T’s Allentown, Pennsylvania wafer fab. The new WE DSP32C has an 80nS instruction cycle, and is claimed to perform at 25MFlops – which implies that a fully-configured Pixel Machine using it will have a burst performance of something like 2Gflops, which should set a heart or two fluttering even over in Japan. To achieve faster speeds, the DSP32C has been implemented in 0.9 micron double layer CMOS technology, making this DSP one of the first microprocessors to be implemented in sub-micron geometries. Evolving from the NMOS device which has been available for a couple of years, it needless to say supports all the features of that part.
Would be in clover
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AT&T is rightly proud of its chip design tools – the company is quicker than most at coming up with new, improved versions of its microprocessors, and if only it could sell the damn things when it has designed them, would be in clover. The company reckons that the computer-aided design tools used to create the DSP32C were the most powerful ever assembled even for an AT&T chip design effort. The design team used an all-symbolic layout system to specify an electrical schematic to plan the physical layout of the chip, a procedure that enabled the team to begin work on the chip before the design rules were finalised. In the future, if an upgrade of the chip to even smaller design rules is desired, much of the layout will be performed automatically by the CAD system, cutting redesign time dramatically, says AT&T, adding that in its opinion no other similarly complex chip has ever been designed with all-symbolic layout. AT&T looks for the new C compiler to get the DSP32 into a much wider range of mainstream applications in the appropriate graphics and image processing, CAD/CAM, scientific computing, and high-end telecommunications fields – the last application of course being the one for which the company really designed the chip. The compatibility between the two generations means that designers will have immediate access to an existing library of applications and will not have to wait for the new DSP32C parts to begin development – they can use a 250nS or 160nS DSP32 now and replace it with the higher-performance, lower power-consumption DSP32C as soon as it is ready.
