Atmel has revealed a new custom architecture for 90nm SiliconCity ASIC development, providing up to 350K gates/mm2, offering customers gate densities in the range of a standard cell ASIC.
SiliconCity Flexible Architecture allows designers to create their own wafer architecture for multiple product variations while reducing customer design time, lowering the NRE and reducing risk through design reuse. The company claims that ASIC development based on the architecture allows for lower mask fees and faster time to market.
Atmel said its patented ASIC technology, Metal Programmable Cell Fabric (MPCF), makes the CAP (customizable microcontroller) family of products, and SiliconCity Flexible Architecture possible. In the case of CAP, Atmel defines the platform with ARM cores and bus subsystems, peripherals and memories. SiliconCity Flexible Architecture leaves the definition of the platform up to the user.
According to the company, by predefining the common embedded core and bus, memory and peripheral mix, the customer has the ability to implement unique IP for multiple products. The architecture gives the customer complete control, while MPCF gives it the flexibility.
MPCF reportedly offers a smaller core cell with better routing. The company claims that the combination of the higher gate density and better routability of MPCF-based SoC results in die sizes that are about half those of previous 130 nm generations.
With MPCF, the cell size is matched to the integer multiple of the routing grid and transistor pitch, which results in no wasted silicon. In addition, contacts and vias are also the same size as metal trace, which eliminates any potential overlap and provides the most effective vertical use of silicon in the design.
These aspects of MPCF make targeting the exact gate size required for the design easier and more cost effective than the typical sea-of-gates architecture common with gate arrays and some early structured ASIC products, said the company.
The company said many existing designs based on a microcontroller and a FPGA may be directly migrated to a SiliconCity Flexible ASIC in 20 weeks from final gate-level netlist with minimal re-engineering and low initial NRE mask charges. Future iterations of designs can be implemented in 8-12 weeks with lower single metal mask NRE charges.
