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October 18, 1998

ARM INTRODUCES ARM10T PROCESSOR CORE DETAILS

By CBR Staff Writer

ARM Holdings Plc has given technical details of its ARM10 Thumb Family processor cores. The Cambridge, UK-based company says that the 400 plus MIPS processors will be aimed at smartphones, personal digital assistants (PDAs) and set-top boxes. The company claims that ARM10T-based chips will offer higher performance than previous ARM chips, especially in the area of graphics, imaging and games. ARM10T processors are designed to offer 400 Dhrystone 2.1 MIPS at 300 MHz, and the company says the core will be portable to 0.25 and 0.18 micron fabrication processes. Mike Miller, executive vice president of business development, says that the major changes over the ARM9 series core design are 4 or 5 new instructions, a new and deeper pipeline and a more sophisticated bus between the chip and the cache. All of which should add functionally and ramp up the speed of chips based on the new design. The core design architecture is designated V5T and it is backwards compatible with the ARM7 and ARM9 series. However, one feature of the new design has already caused controversy. IBM Corp says that the ARM Thumb compressed 16-bit instruction set, which converts 32-bit instructions to 16-bit extensions, is less efficient than its own algorithm-based variable length instruction (VLI) set (CI No 3,518). Miller said that IBM had made some interesting claims and said that ARM had tested out a VLI solution for the new chip but that it had caused problems in the tool chains. However, he declined to comment further on the matter until he had more technical information on Big Blue’s PowerPC core. Initial prototypes of the ARM10T range are expected in mid-1999.

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