ARM has unveiled its AMBA 5 Coherent Hub Interface (CHI) architecture that will support the Cortex-A50 series processors to work in performance, coherent processing hubs to offer high data rates.
The AMBA 5 CHI specification is based on AMBA 4 ACE technology and is used by the ARMv8 architecture-based Cortex-A57 and Cortex-A53 processors as well as the CoreLink DMC-520 Dynamic Memory Controller and CoreLink CCN-504 Cache Coherent Network.
According to the company, the specification has been developed to support high frequency, non-blocking data transfers between multiple fully coherent processors.
ARM Processor Division Marketing and Strategy VP, Noel Hurley, said that the company has worked with many partners across the SoC design ecosystem to allow its silicon partners to rapidly deploy IP and SoCs implementing the AMBA 5 CHI protocol.
"Through early engagement we have enabled our EDA partners to develop a wide range of verification IP, and debugging and performance analysis tools to accelerate the implementation of AMBA 5 CHI based SoCs," Hurley said.
The company claims that the interface allows optimal system performance by supporting distributed level 3 caches, high rates of I/O coherent communication, and Quality of Service (QoS) functionality.
Additionally, the architecture introduces a layered model to enable implementations to separate communication and transport protocols, which allow the optimal trade-off between performance, power and area.
