ArcSys Inc, Sunnyvale, California and Synopsys Inc, Mountain View are claiming to be first to offer a submicron design methodology that reduces time to market and increases the performance of deep submicron integrated circuits. Under the partnership agreement, Synopsys has integrated its synthesis tools with Arcsys’s timing-driven layout tools and will be selling the tools directly to customers. According to Paul Greenfield, Arcsys’s vice-president of European operations, the onus of chip design has now shifted towards its customers. Customers are buying place and routing tools to design chips themselves rather than relying on chip fabricators to do it for them because time to market has become increasingly critical to chip design, said Greenfield. The design methodology incorporates Synopsys’s DC Expert and Floorplan Manager and ArcSys’s ArcCell and ArcGate floor-planning and place and route tools. The chip design, written in VHDL, is read into DC Expert, Synopsys’ synthesis tool which converts the VHDL format into a gate level format. This format is then converted into a floor plan, a physical representation of individual cells within the processor together with the design logic and timing. This floor plan is then re-optimised by the Floorplan Manager. Both companies products are shipping now.
