Apple Computer Inc is hard at work on its second generation of PowerPC Macintoshes under the TNT code name for launch next year, and MacWeek now hears that they will be aimed at all power users, not just at audiovisual users, because Apple has discovered that many people buying its AV models have been doing so simply because they wanted the fastest Mac available, not because they were multimedia junkies. The paper hears that one will be designed for tasks such as mathematical modelling and handling complex relational databases, expected in the first quarter of next year, and the other as a graphics workstation arriving a few months later. Despite the superior performance, they are currently expected to use the existing 80MHz PowerPC 601. Both will use the Peripheral Component Interconnect for their expansion buses where the initial models use NuBus. The high-performance configuration will come with built-in video, bit the graphics workstation model will not, although it will support a range of video boards – Apple is said to have submitted its vision of a PCI-based video board to several manufacturers and asked for bids for making the board under the Apple name. The company is working on application-specific integrated circuits to enhance performance, but it is not certain which will go onto the motherboard and which on the video boards. Chips include one to improve the rate at which the Mac can perform digital-to-analogue conversion to increase QuickTime encoding and decoding by perhaps 30% over the current software version. Another is expected to be dedicated to speeding most drawing tasks so that many operations, including menus popping down and simple colour animations will happen more quickly. The planned three-dimensional extension to QuickDraw is expected to get its own accelerator chip, with a private cache independent from the rest of the system for high-end, high-speed three-dimensional graphics manipul ation. And they are tipped to have an internal Apple RISC Bus as well as Peripheral Component Interconn ect, to link the CPU with caches and main memory; a new chip is said to be being designed to bridge the two buses and maintain performance.
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