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February 29, 1988

APOLLO COMPUTER LAUNCHES ITS 64-BIT PRISM RISC MACHINE

By CBR Staff Writer

Apollo Computer Inc today launches its top-end line of 64-bit RISC processors, promising performance, at between 15 and 30 VAX MIPS for single processors, 60 MIPS to 100 MIPS for multiprocessors, that brings it head-to-head with developments from Sun Microsystems, Motorola Inc and MIPS Computer Inc – as it will need to in order to justify the UKP60,000 entry price. Apollo has coined its own acronym for the new architecture, Prism, for Parallel Reduced Instruction Set Multiprocessing, and it will appear in the form of the Personal Supercomputer – a name cheekily trademarked by Apollo – as a server or Domain Series 10000 workstation in the third quarter 1988. The processor is a seven-chip 1.5 micron set in CMOS, being made by VLSI Technology Inc, Santa Clara and Toshiba Corp, Japan. ECL and BiCMOS versions are in the plan, and the CPU is rated at 35MFLOPS peak, 8MFLOPS on single-precision Linpack. A three-dimensional graphics system using the architecture is due for announcement in the second half of the year. Designed to use one to four processors in symmetrical multiprocessing configurations, the Domain 10000 can have from 8Mb to 128Mb memory – 512Mb when 4Mbit DRAMs become available to replace the current 1Mbit chips – and 3Gb disk. Server prices start at UKP60,000 and workstation configurations, with 19 1024 by 800 display, at UKP65,000. The operating system is Domain/OS, supporting the proprietary Aegis version of Unix System V or Berkeley 4.3, and Apollo promises source code and binary data compatibility with existing Domain products. The company boasts that the products deliver up to 10 times the throughput of Hewlett-Packard and Sun high-performance workstations, nine times the throughput of a Silicon Graphics high-end system, and says 20 hardware and software suppliers have committed to use or support the product. Key features of Prism are a 64-bit data path in the CPU, which includes integer and floating point units, 128Kb cache for instructions, 64Kb for data, 150Mbyte-per-second system bus, and shared virtual memory multiprocessing. The architecture supports both VMEbus and IBM AT bus. Apollo has also incorporated some of the dataflow ideas emerging in minisupercomputers like Multiflow’s Trace family, saying that new compilers detect parallelism in code, helping the CPU to execute up to three in.lh 6 structions in a single 20MHz cycle.

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