But Intel Corp is determined to make itself as fast a moving target as possible, and with the P5 still unannounced, has reiterated its intention to start shipping the follow-on P6 as soon as the fourth quarter of next year, a threat first made in February (CI No 1,869). Executive vice-president Craig Barrett told Dataquest’s Semiconductor Industry Conference in Monterey that the P6 will integrate some 10m transistors, against 1.2 for the 80486 and 3.1 for the P5. The company is still pitching for 100m transistors and 2 GIPS by the year 2000, and says that that kind of performance will be needed for applicatiosn such as handwriting recognition. The P7, the first 64-bit member of the iAPX-86 family, is scheduled for 1994 or 1995, and will be aimed initially at the supercomputer market – taking on the role that had been marked out for the ill-fated 80860, before finding its way into servers and workstations. Our sister paper Unigram.X also hears of a P54, which could be a P5 in 80486 clothing, and the P67, which may be a 1994 transition chip between the P6 and P7. Apparently the P67 will have 64-bit characteristics like a 64-bit EISA extension but most of it will be 32-bit.
