Amkor Technology and Texas Instruments said that they have started producing fine pitch copper pillar flip chip packages, shrinking bump pitch up to 300% compared to current solder bump flip chip technology.
The companies said that the co-developed flip chip packages lowers the packaging costs of integrated circuit (IC) devices with fine pitch input/output (I/O) pad structures of less than 50microns. These also boosts performance, making it ideal for wireless and embedded processing applications based on plated copper pillar bumping and assembly technology.
Tom Thorpe, vice president and manager of external development and manufacturing at Texas Instruments, said: "As chip I/O density increases with each process node, we had to find a way to decrease the distance between pins.
"Working together, Amkor and TI rapidly developed, qualified and deployed a new package platform that will not only address TI’s flip chip package needs for the next decade but will also serve as a game changer for the industry.
"This new packaging technology will drive down the size and cost of semiconductors while boosting performance – a win for TI, Amkor and our customers."
The new lead free technology enables the use of flip chip interconnection at fine pad pitches (50 microns and smaller) using fine pitch copper pillar bumping and a newly developed assembly process.
In addition, this technology acts as the platform interconnect technology for integration with next generation advanced silicon nodes. The fine pitch flip chip layout design methodology reduces substrate layer count as compared to standard area array flip chip, yielding a low cost package offering.
Ken Joyce, president and CEO of Amkor Technology, said: "Amkor and TI worked tirelessly to bring this complex technology to market against a challenging development timeline. Both organisations mobilised significant resources to advance the state of the art for copper pillar bumping, fine pitch interconnect assembly, and advanced packaging.
"We are committed to partnering with TI in applying this new technology on chip scale packages (CSP), conventional package on package (PoP), and next generation TMV PoP configurations."
