Acer Labs Inc has announced a family of chip sets for mid-range personal computer servers and workstations using Pentium, K5 and M1 chips, promising they will give them high-end features. The Genie family has been designed to enable personal computers to offer multitasking, multi-threading and multiprocessing. The company said the Genie brings true symmetric multiprocessing to file servers, high-performance multiprocessor application servers and high-performance workstations, which can not be achieved with shared L2 cache pseudo symmetric multiprocessing architectures. In that type of a system, the addition of another processor does not bring the performance increase that users would expect, Acer asserts. The Genie has been designed to enable systems manufacturers to design a generic high-performance system boards that can support separate boards for different processors types, so minimising the need to redesign boards as new processors become available. The Genie 1600 consists of three highly integrated chips and uses an architecture designed to balance input-output and chip performance for very high throughput. It features a memory bandwidth of 264M-bytes per second and direct memory addressing to 1Gb. At its heart is the company’s 64-bit concurrent bus architecture, performance-enhanced input-output and processor architecture, PCIA, which was originally developed for use with the MIPS Technologies Inc 4000 RISC processor family. The chip set provides full concurrency between all processors and PCI input-output devices, enabling system throughput to increase linearly as processor performance increases. On-chip Error Code Correction provides the required memory protection for high system reliability. The members of the chip set are the M1601, M1609 and M153. The M1601 is a high-performance Modified Exclusive Invalid Share cache controller that supports single or multi-processors. Both Advanced Program Interput Cache and SystemPro multiprocessor interrupt dispatch are supported. It integrates the processor bus controller; dual port high-speed tag static RAM; L2 Modified Exclusive Invalid Share cache controller; high speed data buffer; the host memory bus arbiter; and the host memory bus controller. The M1609 provides Dynamic RAM control and PCI bus bridge function to Genie-based servers and workstations. It integrates a dynamic RAM controller; on-chip error correction code/parity circuits; input-output cache controller; 256 byte writeback input-output cache; PCI bus interface circuits; and memory bus interface circuits. In order to achieve a balance of the system throughput, it uses a serial input-output writeback cache technique to isolate the input-output bus from the memory bus. The M1513 AT/PCI Interface Controller supports a wide range of computer peripheral devices and includes an integrated AT bus controller, an integrated Advanced Program Interput Cache for dual-processor applications, PCI prefetch and on-chip PCI bus arbitration with fixed and rotating priority schemes. Although the family is aimed at high-end business server and engineering applications, it can also be used for a high-performance Windows95, Windows NT or OS/2 desktops or workstations. The first version of the chip set family supports the iAPX-86 architecture of Intel Corp Pentium, Advanced Micro Devices Inc K5 and Cyrix Corp M1. The Genie 1600 System Core Logic chip set is sampling already and is is priced at $55 in 1,000/month quantities.
