IBM has open sourced its POWER ISA (Instruction Set Architecture), and opted to make the OpenPOWER consortium that it leads part of the Linux Foundation.
The decision makes IBM the “only processor vendor and POWER the only architecture with a completely open system stack, from the foundation of the hardware through the software stack”, the company boasted of the decision.
The decision will allow hardware developers to build architectures (not least those based around IBM’s Power9 processor) royalty-free.
IBM also open sourced reference designs for the architecture-agnostic Open Coherent Accelerator Processor Interface (OpenCAPI) and the Open Memory Interface (OMI).(These help maximise memory bandwidth between processors and attached devices; helping to tackle performance bottlenecks for demanding workloads like AI).
The move is an adoption play that comes amid both a rise in the use of the open source RISC-V chip architecture – including by China’s Alibaba, which recently unveiled its first semiconductor based on RISC-V – and the continued dominance of Intel’s x86.
Computer Business Review fired Mendy Furmanek, Director of OpenPOWER Processor Enablement, IBM, some questions about the decision and its impact.
What inspired the decision to open up POWER ISA rights?
We are encouraging a broader community of companies and developers worldwide to adopt it [POWER] and build their own implementations of the POWER architecture. Open sourcing hardware reference designs enable faster adoption of new technologies and accelerates hardware innovation across the ecosystem.
Is IBM not going to take a financial hit on this as a result?
Not at all. Over the past six years, IBM has encouraged the OpenPOWER Foundation’s rapid growth to include nearly 350 members around the world. We have built a strong community with significant capacity for innovation and this is simply the next logical step in strengthening the ecosystem.
Is this a bid to confront the rise of RISC-V?
Quite the contrary. IBM is a member of the RISC-V Foundation. While there could be some overlap between RISC-V and POWER architectures over time, current implementations are focused on different segments of the market, and we believe that there is room in the industry for both architectures to grow.
To accelerate the growth of open hardware, there is open infrastructure and development tools the open communities can and should develop collaboratively. We also believe that there are common building blocks, such as OMI-based memory controllers, which are relevant to both ecosystems.
Can you furnish more details on the “hardware reference designs” you’re contributing? [To the Linux Foundation/open source community]
IBM will contribute multiple other technologies including a soft core implementation of the POWER ISA, as well as reference designs for the architecture-agnostic Open Coherent Accelerator Processor Interface (OpenCAPI) and the Open Memory Interface (OMI).
OpenCAPI and OMI help maximize memory bandwidth between processors and attached devices, critical to overcoming performance bottlenecks for emerging workloads like AI.
Can you paint a bigger picture image of the industry impact you see as a result of this? (Few examples?)
Here are a few examples of hardware solutions that can be built.
> Differentiated heterogeneous systems, built to tackle the challenges of modern workloads, can be realized when integrating these solutions together. This creates value across the industry from hardware to software to system providers.
> Softcore implementations of the POWER ISA could be used in FPGAs or in ASICs
> POWER ISA implementations could be used in server, consumer or embedded applications. An OMI host interface can be used in any ASIC that supports DRAM to reduce the ASIC pincount by ~4x or increase the bandwidth by 4x, while avoiding license payments for embedded memory controller IP.
> It can also be used for a dramatic increase in deep memory bandwidth for future FPGA accelerators.
> OpenCAPI device interface can be used for compute accelerators and advanced IO, such as coherent network and storage controllers, implemented in a FPGA or ASIC to have a high bandwidth coherent interface to any host CPU (as it’s architecture agnostic). Likewise OMI device interface can be used for “in-memory” acceleration solutions implemented in a FPGA or ASIC connected to any host.