Prototypes of the I-Tron industrial variant of Japan’s Tron operating system have been implemented on a number of existing chips, to test the specifications and real-time capabilities, and some have been commercially available in Japan since l986. Hitachi has a product based on the 68000 microprocessor with a very fast – 80 microsecond – response time to external interrupts. It comes with a C language interface library to aid application development, and a task-oriented debugger. Fujitsu has a system based on the 80286 which uses the built-in memory management unit. It implements a superset of the I-Tron specs, with added system calls to support the memory manager. Mitsubishi developed the RX116 microprocessor as a testbed for the I-Tron specification (with added functions) but had to add an external interrupt controller to handle nested interrupts. However, it became the first commercial I-Tron product, linked to a co-processor running MS-DOS, as the RX116 does not have a file system.
64-bit addressing NEC went on to develop a 32-bit implementation for its V60 microprocessor – the 16-bit bus version of the 32-bit V70 – with added access protection and fault tolerant support. Although these implementations worked well enough to be released as commercial products, the full benefit of hardware and software being developed and optimised together will only be seen when the current range of 32-bit CMOS chips become available later this year or early next year. The Tron processor specifications will only really come into their own with a 64-bit architecture: address bus, data bus and registers. The Tron designers are convinced that 32-bit addressing – a 4Gb address space – will soon be made obsolete by increased demand for memory, especially for artificial intelligence applications. And that machines will soon have more than 4Gb of real memory: The capacity of memory devices increases twofold every two years, so today’s 1M memory chip will have developed into a 32M chip by l997. And it will take only 1,024 of these chips to realise a 4 Gigabyte memory. But recognising the limits of current technology, the definition includes subsets for 32-bit and 48-bit architectures, but they are designed to be upgraded to 64 bits. Similarly, the standard system bus, the Tobus, can be expanded to 64 bits. It performs asynchronous transfers, uses a distributed bus arbitration method and is fault tolerant, with functions and self diagnostics. The double and triple redundant bus Tobus is designed to take all the co-processors and support chips that will be needed until higher levels of VLSI integration have been achieved, for example a graphics processor, cache memory management unit, translation lookaside buffer. An I-Tron implementation designed to be used as an embedded controller might have no use for a memory management unit or translation lookaside buffer to implement virtual memory, but would use the space on the chip for a large cache memory to speed context switching (the instruction set contains high-level instructions to support fast context switching) – vital in real-time processing. Other high-level instructions implemented for the I-Tron operating system effeciently manipulate the ready queue and wait queue to further speed up the response time. Similarly, the instruction set for the B-Tron workstation version includes high level instructions to support the bit map processing needed to move and compute data for windows efficiently. Even if a graphics co-processor has to be used for the more advanced graphics processing, using it to control the windows on the screen would tie up a lot of the bandwidth of the Tobus, possibly slowing down memory accesses or input-output. The Tron processor uses two types of instructions. It has normal Complex Instruction Set Computer-type instructions for the high-speed execution of frequently-used instructions. These either use simple addressing modes or involve register-to-register operations such as arithmetic. (The processor has 16 high-speed registers which can be either 32 or preferably 64
bits wide.) The Tron compiler, as part of its optimisations, tries to rewrite each instruction into a short-format RISC-type and recalculate each address into a simple mode. These relatively simple optimisations, done after the more complex structural optimisations, enable the compiler to produce compact object code that executes at high speed. When it comes to the Tron microprocessors (as opposed to the instruction sets, operating systems or simulations) commercial rivalry rears its ugly head and misinformation, obfuscation and inscrutable confusion reign. Either three companies or 50 are developing VLSI parts. They are called the G-Micro/100/200/300 or the M32/H32/F32. And either…. What is certain are the instruction set and five levels of CPU specifications: * Level 0 stipulates the requirements that all Tron processors must satisfy, such as register set, most of the functions of the instructions, and the bit pattern of the instructions. * Level 1 designates requirements that most Tron processors must meet – the only exceptions allowed are special-purpose co processors or auxiliary Tron processors. * Level 2 designates specifications for functions too advanced to be implemented with current technology but will be needed in the future, such as instructions to manipulate and convert multidimensional arrays. * Level X stipulates the additional instructions and resources needed to extend to 48- and 64-bit environments, such as 64-bit arithmetic. * Level 4 contains the rest – anything that has been forgotten, and instructions or resources that turn out to be needed in the l990s, and any control registers or privileged instructions that the extended operating systems turn out to need. Each Tron chip must comply to a certain level, and be compatible, in terms of object code, with chips from other manufacturers in the project. The specifications say nothing about whether a memory management unit, translation lookaside buffer or cache memory should be implemented on the chip, only that the chips must be able to communicate with the Tobus. The specification for the Tron memory manager, (which can be omitted or amended) provides paging and a four-level ring protection, with a 4K-byte page size. Ring protection can be specified for every page. The page table entry has bits to indicate the presence of a page in main memory, reference, modification, the status of ring protection, and read, write and execute protection. The 32-bit version requires a two-level paging table, and partitions the 4Gb address space into two regions: a shared region used mainly by the operating system and an unshared region where the multiple virtual spaces for the application programs are implemented. Mitsubishi’s chip, the M32 or G-Micro/100, satisfies the Level 2 specifications and is designed for embedded systems. Hitachi and Fujitsu have jointly developed a pair of chips for general-purpose computing and supermicros, while Matsushita is developing a family of chips, the first for high-performance workstations. And at least two more companies are believed working on microprocessors.
