If there’s anything that the computer industry doesn’t need, it’s a few more acronyms. But the engineers are hard at work and new computing technology and acronyms seem to be an unavoidable side effect. The two most important new acronyms, at least as far as the AS/400 is concerned, are VLIW and NUMA, Very Long Instruction Word and Non-Uniform Memory Access. VLIW is one technology being explored by researchers in Rochester so IBM can build processors that go beyond the capabilities of its RISC chips. NUMA is a way of coupling AS/400s together that makes clustered systems look like one big AS/400 even though that isn’t the case. Both emerging technologies will enable IBM to build bigger and faster AS/400s. The whole argument behind going to RISC processors is simple, even if getting them to work correctly isn’t. Complex instruction set processors such as those used in the System/38 and most AS/400s have a very ornate set of instructions that they keep in their chip hardware. Complex instruction chips typically have a very high number of instructions, too, which means that they are very big chips.

Pipelining

The idea behind a RISC chip is to limit the number and complexity of chip instructions and force program compilers to assemble complex instructions out of simpler and less numerous instructions. Another feature of most RISC processors, and one that is significant to the AS/400 and IBM’s Very Long Instruction Word development efforts, is pipelining, which enables a RISC processor to perform more than one instruction at a time. The AS/400 RISC processors have five pipelines; on average, they can execute either three or four instructions per CPU clock cycle. Hardware on the RISC chip is what is actually responsible for filling the pipelines to get that average so high (other chips do worse). The effect of pipelining is that it makes a chip look faster than one might guess based only on its clock speed. A Very Long Instruction Word processor will do two things. First, it will take pipelining to the extreme, adding up to as many as 16 or 32 pipelines to a processor. Second, it will push the problem of keeping the pipelines busy off the chip and back out into the program compilers, which will have to sift through gargantuan heaps of instructions and order them so as to keep those 16 or 32 pipelines filled. Because the chip doesn’t have to manage the pipes and because there are more pipes being used, a Very Long Instruction Word processor can get a lot more work done in one cycle than a RISC processor of the same clock speed. IBM says that AS/400s built with Very Long Instruction Word and related compilers will be as much as 12 times faster than RISC processors of similar clock speed. The Very Long Instruction Word processor gets its name from the way instructions are dispatched to the processor. Once 16 or 32 instructions are lined up by the compilers, they are glued together and sent simultaneously to the processor as one long instruction word. Very Long Instruction Word is really a bad name for this technology because it makes it seem like there’s something special about the instructions. There isn’t.

By Timothy Prickett

As if these Very Long Instruction Word processors weren’t enough, the Rochester tecchies are working to try to improve the clustering capabilities of AS/400s to yield even larger single image systems. NUMA, Non-Uniform Memory Access, is a twist on OptiConnect that uses very fast optical links and tricky software to build one very large AS/400 from a network of systems. It is neither a tightly coupled system (like IBM’s current AS/400 multiprocessors, where many processors share the same memory) nor a loosely coupled network (like current OptiConnect, where many processors all have their own memory). With Non-Uniform Memory Access, many processors are linked to share the same memory, but some of it is local and some of it is remote. In effect, computers are linked together through their memory buses, not their input-output buses as is the case with local networks. The trick with Non-Uniform Memory, and one that no vendor has yet mastered, is to balance the way memory is physically configured in the network so that each system has to go to remote memory only about 10% to 20% of the time. Using Non-Uniform Memory, local memory is accessed quickly, while remote memory (which may be physically located on an adjacent system in a network) takes quite a bit longer. Just as with Very Long Instruction Word, IBM has to redesign the AS/400’s compilers, which is always troublesome. Only time will tell if IBM can pull it off, but everyone is hopeful… except for IBM’s competitors, we suppose. While most of IBM’s work in improving AS/400 technology will focus on processor design and system software enhancements, IBM will also be tweaking its other electronic components and peripherals to take advantage of the latest advances. Right now, the memory chips used in AS/400s are among the fastest and most capacious of dynamic RAM chips produced anywhere. One of the reasons that AS/400 memory is much more expensive than that used in personal computers or workstations is that it is expensive to make the faster AS/400 memory chips. Most modern AS/400s use 45nS access time chips; personal computers typically use 60nS chips. The AS/400 has always been the first product line to use IBM’s most advanced memory chips. There is no reason to believe that this trend won’t continue. Currently, IBM has just about run out of room on AS/400 memory boards using 16M-bit chips. While these chips are fine for low-capacity memory boards or chip sockets, they are inappropriate for very capacious boards. The fattest AS/400 memory board for the 530 servers has memory chips stacked four high, welded together and then to the board. IBM doesn’t have any other way to make capacious AS/400 memory boards at the moment.

Wafer fabs

The next generation of DRAM chip technology – 64M-bit chips – won’t be ready for at least another 18 months. IBM has invested billions of dollars in wafer fabs that will be used to produce 64M-bit memory chips. Last August, IBM and Toshiba put up $1,200m for a 64M-bit chip plant to will be built in Manassas, Virginia. This year, IBM will spend another $1,000m on its own 64M-bit chip plant in Essonnes, France. These two plants will make the chips to be used in forthcoming AS/400 memory boards. IBM hasn’t been specific about exactly when that will happen – the technology has to be tested and cost-effective before it gets put into real products. What is clear is that AS/400s will be memory-hungry if IBM goes through with its software enhancements, and they will require 64M-bit memory.

From The Four Hundred, January 1996 Copyright (C) Technology News of America Inc. All rights reserved.