Tera Computer Co will use Taiwan Semiconductor Manufacturing Co as the foundry for the CMOS version of its MTA Multithreaded Architecture chip, to be used in future MTA supercomputers. Tera currently uses a custom designed gallium arsenide CPU – made up from 24 ASICs – which is produced for it by Unisys Corp. Last year, the company turned to Cadence Design Systems Inc to help it produce an integrated CMOS version (CI No 3,140). TSMC says it will produce the 3.61 square centimeter die using 0.25 micron process. Tera plans to phase in CMOS technology over the next couple of years, said Jerry Loa, VP of hardware engineering at Seattle, Washington-based Tera. The company views the recent resurgence of interest in VLIW very long instruction word and EPIC explicitly parallel instruction computing chips -most prominently in Intel Corp’s Merced processor – as an endorsement of its own multi-threaded approach. But, it says such designs will have a few hardware threads, typically four, compared to 128 in Tera’s current design.
