Some of it has already been described in other places, but it is worth taking a closer look at the serial link implementation, called S3.MP that Sun Microsystems Inc has rustled up in its labs. The aim, according to Jeff Rulifson, director of technology development at the company’s Sun Microsystems Computer Corp hardware arm, is to deliver gigabit bi-sectional bandwidth across a mesh of up to 4,000 workstations, networked using a low-cost interconnect: Cray Research Inc supercomputer-type performance at workstation prices, according to the marketing spin. The network, in this case Sun’s existing fibre technology, links hundreds or thousands of nodes supported by an application-specific integrated circuit enabling them to co-operate, with few of the overheads associated with conventional parallel techniques. Wired magazine recently likened those overheads to committee processes which run slower and slower as more people are added because more time is wasted trying to organise everyone. The serial link itself was developed by Milpitas, California-based LSI Logic Corp, which has reduced what would until now have called for a board-level requiring nine expensive Gallium Arsenide chips, down to an inexpensive two-chip CMOS application-specific chip set. A single chip can both transmit and receive instructions and is part of the LSI mission to deliver system-type functions at the chip level. Sun, which is LSI’s first public licensee for the technology – the chip builder claims a bunch of others under non-disclosure agreements – designed a chip around the serial link to meet its hardware requirements, which LSI is fabricating in 0.6 micron technology. Because it takes up the real estate equivalent of only 5,000-odd gates on a microprocessor, Sun expects the technology to be hosted directly on the processor in future. LSI is focused purely on the serial link, everything else above it is the licensee’s concern.
Develop compliance
It will produce other versions for the general market using its 0.5 microm process by the end of the year. The technology is described as a 16-bit serialiser-deserialiser accommodating copper or fibre connections; LSI said it will develop compliance with emerging Fibre Channel Association standards. The routing chip itself does all the checksum and dynamic routing, and interfaces directly to the memory bus. It has two parallel interfaces and four serial links to the parent machines passing messages at speeds between 200nS and 5mS. As such, LSI Logic said the link can be used just as well by servers – reducing clutter on the backplane – as in routers. Although Sun will give the technology to universities to play with, it isn’t clear whether S3.MP will become a commercial product. There is understood to be enormous discussion going on within the company about where it should go for its future shared memory interconnect offering. The issue concerns requirements much further out than the big-pipe, multi-node im plementations expected for initial generations of UltraSparc systems (CI No 2,679). It is not simply a question of choosing a new big bus either, the company emphasised, pointing to the fact that at 1Gbps, S3.MP already runs at least three times as fast as offerings such as Tandem Computers Inc’s 300Mbps TorusNet (CI No 2,590). All traditional message-passing and shared memory mechanisms will fall by the wayside over time in any case, argues Rulifson, who foresees a future in which network controller chips will pass object message bindings between object-oriented kernels on each node at Gigabit-per-second speeds with no global cache coherency or a full-scale shared memory model. It’s the kind of route that IBM Corp will likely take with its SP parallel proce ssors, Rulifson said, adding that there are already two or three programming models supporting S3.MP. Other stuff his team is working on include techniques to bring the cost of MPEG 2 encoding systems – currently at the $200,000 to $300,000 mark – down to $100,000 or less, and radio-type local and wide area network connection
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