Applied Materials has reported a net income of $1.7bn for the third quarter of fiscal 2024 (Q3 FY2024), a 9% increase compared to $1.56bn for the same quarter of the previous year. The company’s revenues, meanwhile, rose by 5% to $6.78bn, with $4.92bn generated by its semiconductor systems unit and $1.58bn in net revenue by its applied global services unit. Applied Materials’ chief executive Gary Dickerson attributed these strong results directly to the ongoing boom in demand for AI services.
“Applied Materials is delivering strong results in 2024 with record revenues in our fiscal third quarter and earnings towards the high end of our guided range,” said the firm’s president and chief executive, Gary Dickerson. “The race for AI leadership is fueling demand for our unique and connected portfolio of products and services, positioning Applied to outperform our markets over the longer term.”
Applied Computing wants AI to go green
In light of these results, Applied Computing emphasised the increasing need for energy-efficient computing driven by AI during its Q3 2024 earnings call, with the firm disclosing its target of improving the performance-per-watt of its chips 10,000-fold over the next 15 years. This, the company added, will necessitate advancements in semiconductor technologies such as Gate-All-Around (GAA) transistors and 3D DRAM.
The demand for High-Bandwidth Memory (HBM) has also surged, significantly contributing to the company’s revenue growth in 2024. Applied Materials forecasts net revenue of approximately $6.93bn, with a possible fluctuation of $400m, for the fourth quarter of fiscal 2024. The company also projects diluted EPS to be between $2 and $2.36 in Q4 FY2024. Sales to China – previously a stalwart for Applied Materials – were also up 27% year-on-year, but down from the previous quarter’s level of 43%.
Advances in semiconductor tech
Last month, the company unveiled materials engineering innovations aimed at enhancing the performance-per-watt of computer systems. These advancements enable copper wiring to scale to the 2nm logic node and beyond.
The new solution is said to reduce resistance by as much as 25%. In addition, the enhanced low-k dielectric material lowers chip capacitance and bolsters logic and DRAM chips for 3D stacking.
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