Sunnyvale, California-based chip maker Advanced Micro Devices Inc, boosted by its recent court success against Intel Corp (CI No 2,151), has been out meeting its customers on a world tour. Not only has it showcased its product offerings including the new high end range of Macro Array CMOS High performance and density, or Mach, devices and recent high-speed programmable logic devices – but has offered its third party Fusion partners a platform and conducted straw polls to assess the demand for new 3V devices among its customers. The new high speed devices are the PALCE 16V8H-5, 20V8H-5 and 22V10H-7 family which has just been released. The family is designed to replace Advanced Micro’s bipolar equivalents and offers customers the important advantage of power savings. CMOS devices are also re-programmable using electrically erasable circuitry, and can pack more circuitry on board than bipolar chips – hence the ‘CE’ in the name which stands for CMOS-Erasable. The 16V8 is functionally compatible with all 20-pin generic array logic devices. It has an external frequency of 125MHz and runs on 115mA – half the supply current of a bipolar device and offers 5nS input-output. It serves as a direct plug-in replacement for Advanced Micro’s PAL 16R8, and most of its PAL 10H8 series, and offers designers the advantage of individually programmable outputs.

Reduce board noise

The 20V8 shares the same architecture but has more input pins. It is functionally compatible with 24-pin generic array logic devices and functions at the same speed as the 16V8 above. The CMOS PALCE22V10, is a more complex device offering greater flexibility, inputs and terms. It uses Advanced Micro’s patented programmable macrocell technology and offers up to 16 product terms per output. Presently it offers 7nS input-output, 5nS set up time, 6nS clock-to-output delay, 91MHz maximum external frequency and operates at 120mA. A faster version is promised soon. AMD says it has been working hard to improve the robustness of its chip designs. For instance, it has eliminated the need for external resistors, by using active pull-ups on inputs and input-ouput pins. This enables designers to leave unconnected pins floating and reduces the number of components on the circuit board. Efforts have also been made to reduce board noise through improved clamping circuitry and the use of overshoot filters on programming pins. And on its fastest devices, Advanced Micro is now using split power supply. This helps eliminate the noise that results from the speedy switching on CMOS devices. For applications where low power consumption is the prime concern, AMD offers its speciality zero-power or ‘ZPAL’. This has transition detectors on its input-output pins enabling it to power down when the supply current drops below 15 micro-amps. When no inputs are detected for 50nS it then enters sleep mode. Advanced Micro offers two ZPALs – the 16V8Z and more complex 22V10Z which are suitable for battery powered applications such as meters and cellular phones. The ‘Mach’ family represents what AMD describes as its ‘mid density’ product range. It is geared at designers needing non volatile, higher density logic than the standard Programmable Array Logic devices and comprise a number of programmable array logic blocks interconnected by a switch matrix. The smallest device in the range is the Mach 1 family’s 44-pin MACH110 with 32 input-outputs and 32 macrocells. The next level up is the Mach 2, which builds on the Mach 1 by doubling the basic amount of logic with the same pin-count, and with an additional buried macrocell added for each output.

By Lynn Stratton

Hence the Mach 210 has 32 input-outputs, 64 macrocells and 32 buried macrocells. According to Advanced Micro, the 210 has proven such a popular architecture that it has been chosen for the first speed and power upgrades. A 10nS version is said to be imminent as is a slower, low power version – where the current will be cut to nearly a quarter of the full power version. A 3.3V version is also being designed – either for power-saving or co

mpatability with high speed, high density 3.3V memories and processors. While on tour, the company has been circulating questionnaires in order to assess customer demand for 3V devices. This has uncovered some interesting findings – for instance the hitherto unknown demand for 3.3V chips from desktop system designers. Apart from power concerns, consistency seems also to be an issue here, with designers preferring not to have to construct composite 5V and 3V boards. Another version of the Mach 210 has also been introduced for asynchronous applications. It essentially the same as the 210 with a modified output macrocell and buried macrocel converted into an input macrocell. And it has been followed by two other families with the synchronous/asyncronous Mach three and four families. These have over 84 leads and 5V on-board programming, which has been implemented with a JTAG circuit. This makes it possible to link the Machs with other JTAG devices for easier board testing. There are two Mach 3 devices – the Mach355 which has 96 input-output pins and 96 macrocells and the Mach 365 which has 128 input-output pins and 128 macrocells. The newly announced Mach 4 family is the same as the Mach 3 but with twice as many output/buried macrocells and an additional input cell for each input-output pin. The 435 features 5,000 gates, has eight PAL33V16 logic blocks controlled by a high speed central switch matrix, 128 synchronous or asynchronous configurable macrocells and 15nS pin to pin delays. The multi-tiered switch matrices give 100% routability with over 80% logic utilisation, enabling logic to be changed while retaining old pin-outs and performance. The enhanced logic allocator gives up to 20 product terms per macrocell and a more flexible synchronous and asynchronous macrocell structure. The macrocells can be driven by up to 20 product terms in synchronous mode, 18 in asynchronous with both types of design integrated within the same device. Each of the eight programmable array logic blocks has a 2:1 input to macrocell ratio giving the ability to handle up to 33 input functions. This makes it suited to 32-its microprocessor and address decoding applications. It can be used for a range of high speed control and logic functions, in workstations, RISC microprocessor motherboards, networking, graphics, industrial controllers.

Design tools

It is available from AMD’s distribution network, in an 84-pin PLCC package for UKP31.50. Advanced Micro is also offering an entry level design tool, MachXL, for UKP235. Third party design tool support includes Colorado-based Minc Inc’s PLDesigner-XL and Data I/O’s ABELsoftware – available in the UK from Direct Insight Ltd of Lutterworth, Leicestershire. Development for third party environments such as Mentor Graphics, Cadence Design Systems, Viewlogic Systems, Logical Devices and OrCAD is expected this summer. Programming support is available from AMD’s FusionPLD partners including Houston-based BP Microsystems Inc. The Fusion scheme has been set up by AMD to provide designers with the broadest range of tools possible for each device. AMD offers only an entry level design tool – a personal computer-based system called Palasm – preferring to concentrate its efforts on chip design. Suppliers of design tools include Capilano Computing and IsData GmbH, and Synopsys Inc is among the computer aided design software suppliers. Simulation and modelling systems tools are available from Aldec Co, Logic Modelling Corp, Productivity Through Automation and Teradyne Systems. Advin Systems, Micropross, SMS North America, Stag Microsystems and Systems General supply programming software while Acugen Software, Computer Integrated Network Analysis and iNt GmbH provide testing software. Finally, Exatron Automatic Test Equipment supply test hardware.