Having taken the dominant position in the market for the building block chip sets that make designing MS-DOS and OS/2 personal computers easy, Chips & Technologies Inc, San Jose is moving up-market with a multi-processor architecture designed to support up to six reduced or complex instruction set microprocessors and to facilitate building machines that combine high computer performance with good input-output transaction throughput. Called the Multi-Processor Architecture EXtension System Platform, or M/PAX, the symmetrical multi-processor architecture supports two to six processors – the first version of the chips is for the 80486, but others are planned. Raw performance can be increased by adding more and faster microprocessors, input-output by adding channels. As well as being processor-, the architecture is bus-independent and combines VLSI hardware, integrated software, and design support. The first generation M/PAX product – the CS9239 – enables up to six 80486 microprocessors to run concurrently for close to 70 MIPS performance, and consists of 92C397 Cache Control Unit, 92C390 Cache Directory Comparator, and two 92C395 Processor Data Switches. The Processor Module cache controller supports up to 1Mb of fast static RAM cache and up to six can be designed into a system. The System Memory Module uses a 92C392 System Control Unit and two 92C395 ECC Logic devices and is critical in ensuring a tightly coupled multi-processor as well as supporting up to 256Mb memory. The CS9239 Input-Output Subsystem delivers bandwidth, bus compatibility and peripheral logic and consists of the 92C393 DMA Controller and two 92C395 Data Switches, and directly communicates with up to eight SCSI ports. The CS9239 modules can be designed in either a motherboard configuration or as plug-in adaptors, or combinations thereof. The CS9239 is currently sampling to beta sites, broad sampling will start in April, with volume set for July. In 100- up quantities, a four proc essor CS9239 is $960; dual and uniprocessor versions are $480 and $275 respect ively. A four processor implementation set has two 92C392 System Control Un its, two 92C393 DMA Con trollers, four 92C397 Cache Controllers, four 92C930 Cache Directory Comparat ors, and 16 92C395 Process or Data and DMA Data Switches and ECC Logic devices.
