With its new IA-64 architecture, beginning with Merced, Intel Corp says its main aim was to improve upon the capabilities of today’s architectures by using extensive parallelization techniques, high floating point performance and 64-bit addressing. But even though it intends to carry on with a separate development path for its current 32-bit architectures with processors such as Foster, Intel still couldn’t afford to abandon compatibility with the huge Pentium applications base for the IA-64. And its development partner, Hewlett-Packard Co also needed to provide an easy migration path for its own base of PA-RISC users.
Earlier this week, Intel outlined the compatibility features within the IA-64, claiming full binary compatibility with IA-32 in the processor hardware, and binary compatibility through software translation for PA-RISC. That doesn’t mean existing 32-bit applications will run any faster on Merced without optimization. Ron Curry, director of marketing, IA-64 processor division, said that Intel anticipated that existing applications will run about the speed of the volume IA-32 chips shipping at the time.
IA-64 uses a different instruction decoder within the chip to handle IA-32 applications, and shares the same registers – at least eight of them (Pentium family chips have eight registers, compared to the IA-64’s 256, 128 of them floating point). Intel’s MMX and SSE multimedia instructions continue to be supported. Non-optimized, 32-bit applications can be run using a 32-bit operating system, or can share 64-bit operating system with specially written or optimized applications.
For PA-RISC compatibility, HP has come up with what it calls dynamic translation technology. Jim Carlson, director of worldwide IA-64 systems marketing at HP, said the development had been treated as a virtual processor, using the same tests as on the real PA-64. Bundled within HP-UX, the dynamic translation is invoked automatically once it’s needed, and uses a translate once, use many model to boost performance. Once a translation is performed it is kept in cache memory, and the next time it is used will run at native speeds, said Carlson. HP also says it worked with Intel to provide a one-to-one semantic mapping of instructions between PA-RISC and IA-64. HP’s MAX1 multimedia extensions are also supported.
Carlson said he expected that many PA-RISC programs would not be ported over to the new architecture, but left to use the binary translator. He said some HP customers were still using code from the company’s previous generation of processors, using similar translation techniques. But application developers who wish to use the extended registers, memory management, and new instructions, such as the combined a*b+c=d multiply-accumulate floating point instruction, will have to start porting. A giant Application Architecture Guide for IA-64 is now available for download from these Intel and HP websites http://developer.intel.com/design/ia64/index.htm or http://www.hp.com/go/ia64.
