By Timothy Prickett Morgan
Big Blue has begun whispering a little about the fall line-up in the RS/6000 Unix business, and it looks like it is on track to add the 24-way RS/6000 Pulsar server by September or October. The Pulsar servers are follow-ons to the RS/6000 S7A and H70 servers, which use up to twelve 262MHz or four 340MHz 64-bit PowerPC Northstar processors respectively. IBM isn’t saying officially that the machines will use the Pulsar chips, which will be the first RS/600 processors to use IBM’s CMOS-7S fabrication process, but sources within IBM’s AS/400 division say that the follow-on to Pulsar, the I-Star chips, will not come out until early to mid 2000 and that they will debut first in the AS/400, not the RS/6000.
That leaves Pulsar as the only choice as a faster 64-bit PowerPC processor on the roadmap for delivery by year’s end. IBM is also not telling exactly what the clock speed on the Pulsar part will be. All that Tim Dougherty, e-business product manager at IBM’s RS/6000 division, will say is that the 24-way S80, as the Pulsar servers will be branded, will have between two and three times the aggregate processing capacity of the current S7A Northstars. Right now, it looks like the Pulsars will run at between 450MHz and 525MHz, mainly because IBM won’t hit higher speeds until it announces the I-Stars next year, which will run at 560MHz thanks to the extra clock speeds that are enabled through the use of IBM’s other advanced chip technology, silicon-on insulator. The Pulsar chip is expected to have all the same basic design features as the Northstar chip: two integer units and a floating point unit capable of processing one floating point operating per cycle.
Dougherty hinted that the S80 will include advanced smart caching algorithms (which made their debuts in the RS/6000 F50, H50 and H70 servers as well as in the low-end AS/400e model 170 servers, which like the H70 also use Northstar chips) as well as much- improved SMP algorithms. IBM says that its smart caching algorithms allow its PowerPC and Power series of processors to get the same kind of performance out of machines with half or even a quarter of the L2 cache memory of a similarly powerful set-up from its competitors.
Existing Northstar and future Pulsar processors include another technology called hardware-assisted multithreading that also improves performance. The basic idea is to have two sets of registers in the processor to support two independent instruction streams. That way, when one stream makes a request for data and it is not in L1 cache (and therefore has to be fetched from L2 cache, main memory or, worse yet, disks), the other stream goes on processing even though the first stream has stalled. In a Northstar processor, an L1 cache miss eats up a minimum of five cycles, but switching to another instruction stream only takes three cycles. IBM isn’t being specific about what new SMP techniques it has developed, but has suggested that it will be able to get much better SMP ratios on the Pulsar servers than it has been able to attain with past RS/6000s. Moreover, AIX 4.3.3, which will ship on the S80s, will include performance tweaks, too. Add all of this up, and IBM could get a total of triple the performance of the S7A Northstars, with about 65% of that improvement coming from the faster processors and twice the main memory (up to 64Gb from 32Gb of the S7A), 25% coming from the increased number of processors and another 10% coming from tweaks in the AIX 4.3.3 kernel.
Last year when it announced the Power3 line of two-way workstations and servers, IBM hinted that it expected to be shipping four-way Power3-II workstations and servers by around the same as the S80. IBMers we spoke to would not confirm or deny the Power3-II schedule, but did caution us that it might not be wise to expect the S80 and Power3-II announcements to occur simultaneously. What is holding up the Power3-II processors, the four-way motherboards for RS/6000 workstations and servers, and their related eight-way Nighthawk Power3-II nodes is not known. Previously, IBM has said that it hopes to ship all of these products before the end of the year. The Power3-II chip uses the same CMOS-7S copper process as the Pulsar chip, and is expected to run at 300MHz to 400MHz, providing from 50% to 100% more oomph than the current 200MHz Power3 chip. The Power3-II is the cornerstone of IBM’s expanding supercomputer business, and it is vital that it is not delayed coming to market.
In addition to all this server and workstation stuff, IBM hinted that there may be some RS/6000-related storage announcements. This could mean that IBM is adding function to the Tarpon storage arrays as it ships the Shark mainframe arrays that are based on the Tarpon design. Most likely, IBM will have some added StorWatch software functionality and a more clear storage area network story to tell. This could happen within a few weeks or as late as September or October, if it happens at all.
