Hewlett-Packard Co’s plan for Very Long Instruction Word processors (CI No 2,322) is basically an attempt to bring back the good old days when RISC processors were simple things. Over the last few years, with the search for ever more speed, RISC processors have become inexorably more complex, with superscalar techniques taking up silicon real-estate in the quest to increase the number of instructions executed during each cycle. And the processors are set to get even more complex: the next generation or RISC chips promises speculative execution with one part of the processor executing potential program branches, on the off-chance that the main application will need the results at a later date.
Compiler writers
With its proposed Very Long Instruction Word architecture, Hewlett is aiming to move all this complexity off the chip and dump it in the laps of its compiler writers, which it says, are among the best in the business. The proposed PA-9000 processor then, should be a relatively simple affair – lacking all of the sophisticated superscalar support circuitry cluttering up other chips. What it will have, however, is a series of specialised processing units that operate independently and in parallel. The aforementioned Very Long Instruction Word is actually a string of conventional Precision Architecture RISC-type instructions, chosen by the compiler to be suitable for keeping these units busily executing in parallel. The Word is submitted to the processor, and with a single crank of the handle all of its constituent instructions are executed. The term Very Long Instruction Word is something of a misnomer, since it leaves the impression that the processor has an instruction set composed of a handful of very long instructions – which would imply a very complex instruction set: in fact the instruction set is perfectly straightforward, and it is the compiler that creates the aforesaid Very Long Instruction Word. Hewlett-Packard is hoping to get anything from four to 20 instructions executed per cycle to produce raw throughputs in the Giga-instructions per second range.
By Chris Rose
The traditional problem with the Very Long Instruction Word approach is the intimacy required between compiler and hardware. To parallelise the instructions, the software needs to know exactly what processing units are present in the chip, and how they are related to each other. This close coupling runs counter to the demands of portable software. To provide a degree of portability Hewlett-Packard is planning two-stage compilers, which initially produce an intermediate or ‘meta code’. This code is translated into the finished machine code on the fly, as it is loaded onto the processor to execute. The company isn’t planning to have actual machines ready until the end of the decade, but it is already pondering how to move its software base to the new architecture. One approach under consideration is a compiler that outputs dual binaries conventional Precision Architecture RISC and Very Long Instruction Word. Another approach is binary translation where a Precision RISC binary is run through a software translator that spits out a Very Long Instruction Word-format binary. Hewlett-Packard’s Joel Birnbaum, the original architect of the Precision Architecture RISC, back in the days when it was still called Spectrum (you’d forgotten that, hadn’t you…) and now senior vice-president and head of Hewlett-Packard Laboratories, said at a recent presentation: Our experiments indicate that it [Very Long Instruction Word] will be a superior target for binary translation and that means that we can produce a seamless migration from PA-RISC and perhaps other architectures. The mention of other architectures is an intriguing addendum, about which the company is keeping mum, but on the Precision Architecture side it seems confident that its knowledge of the PA-RISC architecture will enable it to produce simple and efficient translators for the new chips.
Sensitively
Birnbaum dismisses scepticism over Very Long Instruction Word’s applicability for commerci
al processing, and argues that the sceptics raised the same queries over the original Precision Architecture RISC (in the event, that worked perfectly, and it was the problems of creating an appropriate input-output subsystem for the HP 3000 versions of the RISC processor that caused all the headaches and confronted Hewlett with a very uncomfortable transition from its old 16-bit complex instruction set HP 3000s – a troubled transition, it has to be said, that was handled so sensitively by the company that it succeeded in retaining the loyalty of the HP 3000 base against all odds, to the point where its approach should be captured in a text book for others faced with difficult transitions). The company’s planned Very Long Instruction Word processors are inherently parallel, and are being designed to work in multiprocessor configurations – Today many question the application of the VLIW concepts to transaction processing; we expect to prove them wrong again Birnbaum says confidently. He’d better be right, but Hewlett-Packard has made a habit of defying the sceptics and turning out to be right over the past decade.
