Mentor Graphics announced that Fujitsu Semiconductor has incorporated Calibre physical verification and design for manufacturing (DFM) capabilities, enabling flow for all Fujitsu Semiconductor projects, including its analogue and digital designs.
Fujitsu Semiconductor and electronic hardware and software design offerings provider Mentor Graphics are working together to enhance Fujitsu Semiconductor’s DFM methodology by incorporating the SmartFill tool at advanced process nodes.
Calibre SmartFill tool produces a layout that is robust with fewer manufacturing and post-fill induced timing issues by optimising fill shapes for multiple objectives and across multiple layers.
The Calibre Pattern Matching offering provides automatic pattern capturing capability to create multi-dimensional layout verification rules and the Calibre Automatic Waivers system allows information about approved design rule waivers to be included directly in the design database, automatically eliminating spurious DRC violations.
The Calibre PERC product enhances overall design reliability by providing a fast verification environment to check design constraints related to electrostatic discharge (ESD), latch-up and other analogue design factors that previously had to be checked through visual inspections.
Mentor Graphics Design-to-Silicon division vice-president and general manager Joseph Sawicki said Mentor is continuously striving to provide offerings that help the customers address the dual challenges of exploding design complexity and shorter market windows.
"We are pleased that Fujitsu Semiconductor has expanded its use of Calibre to resolve these issues in physical verification and DFM at advanced process nodes," said Sawicki.
