Currently number three in signal processors, with about 15% of the market behind Texas Instruments Inc, 40% and AT&T Corp, 30%, Motorola Inc wants to get to the top of the tree, and to that end has launched what it reckons is the fastest signal processing chip available. The 24-bit DSP56300 core is in alpha and beta tests with a handful of companies, including British Telecommunications Plc and Dialogic Corp and Motorola tells Reuters that every company that tested Motorola’s new chip has placed orders. First part is the DSP56301, which executes one instruction per clock cycle but retains compatibility with the DSP5600 family. It is initially available at 66 MIPS and 66MHz, with an 80MHz version set for second quarter 1996. The part is already being designed into wireless infrastructure, videoconferencing, multi-line speech, data and facsimile processing, Asynchronous Digital Subscriber Loop, Asynchronous Transfer Mode and Integrated Services Digital Network systems, Motorola claims. The products use low power, fully static CMOS designs, so users can throttle back the internal clock speed from 80MHz to zero. Initial versions run at 3.0V to 3.6V; 2.7V and 1.8V versions are planned. The family has a highly parallel instruction set controlling four concurrent execution units: the Arithmetic Logic Unit, the Address Generation Unit, the Program Control Unit and the Direct Memory Access Unit. It features a fully pipelined 24 by 24-bit parallel multiply-accumulator with a 56-bit parallel barrel shifter providing single-clock-cycle throughput. The instruction cache provides hardware cache management, and implements no access penalty for cache misses. It configures 1K-words of program memory to instruction cache and enables the user to lock or flush individual sectors. It contains a total of 4K-word program memory, reconfigurable to provide 3K-words of program memory and 1K-word of instruction cache. No prices.
