A committee led by Synopsys Inc is attempting to promote the firm’s VERA hardware verification language verification language as an open standard for system-on-a-chip design. The VERA Steering Committee is made up of Cisco Computer Corp, AMD Inc, Hewlett-Packard Co and ARM Holdings Plc among others.
Chris Dace, corporate marketing manager at Synopsys, says that verification is the consistently the most critical issue concerning the speed of system-on-a-chip design. Designers have turned towards proprietary optimized verification languages for all stages of integrated circuit design but this has meant a profusion of separate EDA tools and several languages for designers to learn. The VERA group is trying to promote the language as a stable environment that will allow design tool vendors to use one high level language.
Dace says that the language will benefit designers because it cuts the amount of test bed code required and allows simulators and emulators to link to the test bed equipment at a consistent speed through the VERA application programming interface. The first Steering Committee meeting took place in Santa Clara, California on April 7 and the meetings are quarterly. Dace estimates that the first modifications to the language as a result of the meeting will occur in around six months time.
