Two design tools for integrated circuits have been unveiled that will propel chip design into a higher plane – at least that’s what their developer, Mountain View-based Synopsys Inc believes. It says its products, DesignSource and HDL Advisor, offer designers a similar ‘look’ to previous tools but a very different ‘feel’; Synopsys says that people that have used beta versions of the products say designing with them feels like building in code. Currently, integrated circuit designers create Hardware Definitiona Language, HDL, constructs and use synthesis tools to restructure the code into the gate design. At this point it is quite difficult for the designer to relate the gate design back to the code she has written. Essentially, the two Synopsis tools have been created to enable designers to relate code to gate arrays, level by level, step by step, and to do this without synthesis or simulation.

Intuitive understanding

Synopsys says experienced designers eventually learn to do this, but DesignSource and HDL Advisor cut out the years needed to gain this intuitive understanding of how written code translates into Boolean logic. Between the two tools, DesignSource and HDL Advisor, a designer can capture all the descriptions and constraints of a design and analyse the HDL code before synthesis and after synthesis. Both tools are based on HDL semantics, the significance of which is that although there are other schematic capture programs, these cannot relate the graphical display to the hardware code; Synopsys’s tools display every element of the design graphically and every element has a one to one relationship with the textual HDL representation of that element. In this way designers can alter designs far more quickly and any changes made at any point in the programs is propagated throughout the design automatically. As Synopsys puts it, the tools raise the level of analysis capabilities. Both products are Unix-based and have Windows-style interfaces. Synopsys reckons DesignSource halves the time taken to capture all information relating to a chip’s design and HDL Advisor halves the number of iterations a designer would go through before reaching the finished design. The company claims these products are successful and attributes this to the fact that they have been developed from the top down, the language, rather than from the bottom up. To make high level design an efficient concept, Synopsys says it is essential to capture all the source information and display it in a single view; no mean feat given that a medium-sized ASIC will have around 30 modules, that is different sections of the actual chip design, each of which will have at least 16 different elements, that is anything attributable to that section of the design, resulting in around 500 different files. Within DesignSource there is the Hierachy Editor and Structural Editor; this product is not yet in beta test and is not expected to be ready until August.

By Maya Anaokar

However, Synposys says the Hierachy Editor shows the complete design, things like ports, pins and nets, with all the sub-directories and associated information, in one report enabling designers to swap, add, explore alternative configurations or attach scripts and generally play around with the design. The automatic inheritance of attributes across connected objects means changes made are propagated through the design. It has logical library support that provides structured management of data design so that designs can be tracked. The Structural Editor which looks like other schematic capture tools already in the market, says Synopsys, enables the designer to relate any schematic directly back to code. This means that the graphics can be altered and the code will be automatically updated and changes propagated throughout the design. Synopsys adds that semantic checks can be done on the fly. Also DesignSource can be used to drive any other design processes such as synthesis, simulation and so on. The other product is HDL Advisor, a tool with two real-time an

alysis engines, designed to help designers to evaluate the HDL source code before simulation and synthesis. Before simulation it analyses code written for Boolean logic, interconnections such as fan in, fan out, tracing, hierarchy boundarys, and component count, which is based on Boolean representations of the circuit that has been designed, to identify any gross problems in the code. At this point it does not give exact information but what it can show a designer, for example, are the number of gates of logic. So if the designer is aiming for 10 gates and at one point there are 25, the designer can amend that bit only. Once changes at this level have been completed, the design can b e synthesised and the correlation engine analyses that gate level information, studying timing, area and power, and to a lesser extent capacitance. This analysis can be directly related to the HDL each gate is specified by. HDL Advisor, however, cannot predict what synthesis tools will do to the design, although there are plans for such a trick in the future. The tool displays the information graphically as histograms. Within HDL Advisor, users can examine critical paths, explore interconnections and alternative paths and trace sources using the Path Browser which offers annotated analysis on HDL, Boolean logic structure and path tracing on source code; a user selects an object and the coressponding line of HDL is displayed. Once HDL Advisor has done its bit, DesignSource can launch and control a VSS simulation directly from source. And after simulation, DesignSource can also launch Design Compiler. After synthesis, DesignSource will automatically generate a design for verification. Editors from other companies could be used with the suite but as there is no direct correlation with HDL, Synopsys says code would have to be generated, which in itself is not that helpful, and the back annotation path provided by Path Browser would be missing.

Process

But Synopsis says anything that produces HDL or Verilog could be used with this suite. This means designers could use the products part way through a design process. Synopsys is working on specialised editors in the future. Together, DesignSource and HDL Advisor, cost $42,500. HDL Advisor alone costs $30,000 and DesignSource $21,250. HDL Advisor is out at US beta test sites and will be available from May. At that time evaluation copies of DesignSource will be available; DesignSource will ship in August. Synopsys says it plans to develop additional products such as specialised editors for DesignSource and estimation technology for HDL Advisor, although it has no time-frame for this. Synopsys, an acronym for Synthesis and Optimisation Systems, went public in 1992 (CI No 1,842) and claims to have 75% of the market for synthesis tools. This year’s first quarter showed a profits up 43% at $7.5m.