STMicroelectronics has unveiled 32nm technology platform for the design and development of application-specific integrated circuits (ASICs) for networking apps.
Central to the new 32nm SoC design platform, which implements ST’s 32LPH (Low-Power High-performance) process technology, is the first Serialiser-Deserialiser (SerDes) IP available in 32nm ‘bulk’ silicon, the company said.
The company said that the new platform is designed to accelerate the development of NxG networking ASICs used in applications such as enterprise switches, routers and servers as well as optical cross-connect and wireless infrastructure applications.
According to STMicroelectronics, the SerDes IP, called S12 IP is key for the development of ASICs for networking apps and enables chip-to-chip, chip-to-module and backplane communications in networking equipment designs. The 32LPH design platform, based on the 32nm High-K Metal Gate process, supports up to 10 metallisation layers to increase routing efficiency and incorporates specific IP and devices.
A SerDes is normally integrated multiple times (often up to 200) in a single ASIC chip. It enables serial communication between ICs or ASICs on the same electronic printed-circuit board; ASICs and the optical module, which links to remote equipment; ASICs and physical interface module; or ASICs and the system backplane.
Riccardo Ferrari, group vice president and general manager for networking and storage division at ST, said: With the introduction of the 32LPH platform, ST is enabling the next generation of equipment for communication infrastructure applications, which requires highly integrated ASICs that can satisfy the increasing demand in performance, while also meeting extremely challenging power consumption and silicon integration goals.”
The first ASIC prototypes implemented in ST’s 32LPH process technology are expected early in 2011 with production ramp-up in the second half of 2011.
