It looks untidy at first glance, but Silicon Graphics Inc’s acquisition of Cray Research Inc gives it access to the Eagan, Minnesota company’s supercomputer franchise and its 500Mbps scalable interconnect. Cray has 51% of the $297m market for systems above $5m, many of which are installed at secretive government and research agencies, and a healthy $437m order book. Silicon Graphics, now competing with other RISC server vendors’ technologies, is preparing its own high-end offering, currently dubbed Lego, that will accommodate 200 CPUs or more this summer. Silicon Graphics will use the Cray Three-Dimensional Torus interconnect as a building block to accommodate up to 1,000 or more processors thereafter. As expected (CI No 2,813), Thinking Machines Corp will also begin selling a version of its GlobalWorks parallel application software for connecting multiple Silicon Graphics workstations as one processing node. The Silicon Graphics-Cray combination looks messy because Cray currently uses SuperSparc (soon UltraSparc) RISCs in its Solaris-based symmetric multiprocessing servers and Alpha RISCs in its T3D and T3E massively parallel systems. Silicon Graphics is keeper of the MIPS Technologies Inc R-series design. Cray has always said that the Alpha was in no way a lock-in and that it had written the code base in such a way that it could switch to a different RISC with a minimum of disruption. It will begin the move to next generation versions of the MIPS R10000 from 1998, processors it will help design on its Alpha-based simulation systems.
Product lines won’t merge
The R10000 follow-ons will be implemented in different versions for Silicon Graphics’s games console-to-supercomputer requirements. Cray’s migration should be complete by 2000, though both companies make it clear the Silicon Graphics and Cray product lines won’t merge into single product offerings. In the meantime, Cray is preparing new versions of its symmetric multiprocessing, parallel and supercomputer products for the second half of the year. Silicon Graphics and Cray will work to implement a common programming model across their architectures and integrate their Irix and Unicos Unixes. Under the two-part deal, Silicon Graphics Inc is paying $576m, or $30 per share cash for 75% of the Cray Research Inc shares outstanding and once Silicon Graphics has control, the balance of the Cray shares will be swapped for its own shares on a one-for-one basis, expected to represent around 3.5% of Silicon Graphics’s outstanding stock, for a total cost of $731m. The deal will be closed in Silicon Graphics’s fiscal fourth quarter ending June 1996, when the company expects to take a non-cash charge on the deal of $50m to $100m. Silicon Graphics is on target for turnover of almost $3,000m this fiscal year to June 30. Cray has been looking for a partner such as Silicon Graphics for some time. After losing $226m after $188m in charges last year on sales that plummeted 27% to $676m, its blue-chip government customers were apparently loath to give more business to the company on grounds that it might not survive for the term of the contract. Its says it will be profitable this financial year. Cray claims 800 installations, 25% up on last year, with 40% of them new customers. The combined Silicon Graphics-Cray will hold an estimated 43% of the $1,900m high-performance supercomputer market, according to Gary Smaby’s Smaby Group Inc in Minneapolis; it is interesting to note that Cray also did better than Silicon Graphics in the $500,000-to-$1m market last year. Silicon Graphics will retain use of the Cray name, which it describes as US national asset, and will even release Silicon Graphics products under the brand. Sales and research and development units will be merged over time although there will be no word on restructuring or how existing Cray partners will be handled until Silicon Graphics gets control. Silicon Graphics has 7,200 employees, Cray has 3,700. One option of course would be to sell the Sparc-based server line to Sun Microsystems Inc. Cray chief ex
ecutive Phil Samper – one-time president of Sun’s Sun Microsystems Computer Corp hardware unit – isn’t expected to stay on after the deal closes.
Similarities with R-series may point future of Alpha
Perhaps opening the door to the possibility of future consolidation in the RISC microprocessor world, Silicon Graphics Inc was last week highlighting the similarities between its R- series RISC and the Digital Equipment Corp Alpha designs. DEC of course relied on a MIPS variant as a stop-gap for two or three years while it rushed to complete the Alpha design.
Cray Torus interconnect is processor-independent
Cray Research Inc says that its Three-Dimensional Torus bi- directional mesh interconnect, in which prospective parent Silicon Graphics Inc is interested – it currently connects up to 2,048 Alpha RISCs in a T3E massively parallel system – is much faster and ultimately more scalable than multi-stage interconnects such as IBM Corp’s Vulcan switch. Currently operating at a hardware latency of one microsecond and at up to 500Mbps data bandwidth, the interconnect is organised into macro (processor and support shell) and micro architecture technology components specifically so it can be implemented in conjunction with non-Alpha processors. Indeed the idea, Cray says, was to move the interconnect over to whichever generation of processors provided the best performance at a given time. The interconnect is not specifically tied to the PE Processing Element configuration of T3E’s system design either. The interconnect, Cray says, is a classic shared everything, Non Uniform Memory Access Multiple Instruction Multiple Data topology. Although a processor can access all memory, either locally or remotely, as if it were its own, Non-Uniform Memory Access programming models must still understand the memory hierarchy in which instructions will be processed more quickly (even if only a microsecond) by a CPU’s local memory than by a distributed processor. Speed improvements are most likely to occur at the data bandwidth level – as they were between the T3D (Alpha 21064) and T3E (21164) system implementation – since the one microsecond hardware latency, the time it takes to send a message between processors, is not a bottleneck.
