MIPS Technologies Inc has rolled out the first implementations of its MIPS32 family, with entry-level silicon, a core aimed at networking hardware applications and a high-end core optimized for Windows CE-based devices. MIPS is aiming to sell the cores to foundry and ASIC vendors as well as directly to OEM customers to be used in devices from handhelds and low-end set-top boxes to routers and switches.
The 4K cores all share features from previous generations of MIPS cores as well as extensions that began life as custom features added by specific customers. The generic MIPS32 4K core runs at clock speeds of between 150MHz and 225MHz, with a power consumption rating of less than 1 milliwat per megahertz at a 0.25 micron process rule. When the cores are produced at 0.18 micron, MIPS expects the clock-speeds to increase to 200MHz to 280MHz and the power consumption to halve. The cores – including the entry-level 4Kp have some form of multiply and accumulate unit (MAC). According, to David Courtright, director of core engineering, this is to ensure compatibility across the range. A redesigned pipeline has been implemented in all the designs to make sure that the cores work with generic memory chips. MIPS has also designed a new front side bus interface, dubbed ‘Beer’ for the cores, claiming that there was no industry standard that it could adopt. The bus will also be used in its 5K Opal 64-bit cores.
However, the cores can be configured with different size caches – between 0 and 16Kb – different versions of the memory management unit (MMU) and different register sets, depending on the compute power, power consumption and die size requirements. The network hardware optimized 4Km comes with a high-performance, 32 by 16 MAC unit. While the higher-end 4Kc features an MMU that features a 32-entry Translation Look-aside Buffer (TLB) – a table matching virtual addresses to physical addresses. This feature is essential for devices that use the Windows CE operating system.
