MIPS Computers’ visiting fireman outlines state of play in battle to outdo the Sparc
John Mashey, MIPS Computer Systems’ vice-president of systems technology was in the UK last week – first stop on a round-the-world mission to spread the gospel according to MIPS. The acknowledged trouble-shooter and jack-of-all-trades at the Sunnyvale, California-based chip designer brought with him missives on the struggle for ECL, the imminent arrival of the R4000, the end of the big endian-little endian schism and the direction of the Systems Performance Evaluation Council – as well as teasers on the speculation about a version of OS/2 to run on the R-series RISCs. MIPS’ R6000 ECL RISC project has been dogged by problems to the extent that DEC killed its plans to introduce R6000 versions of its DECstation Ultrix workstations at the end of the summer. Mashey is confident that the future of the processor is now assured – although the failure to produce good parts put the whole project in jeopardy during the summer it was touch and go, he says. Indeed the Sunnyvale, California-based company has hundreds of thousands of pounds worth of machines lying around now, waiting for the CPU element in the three-chip set to arrive – the floating-point and cache elements have been in place for some time now. MIPS’ next generation CMOS part – the R4000 – will be revealed pretty soon, says Mashey. Initially it’ll be positioned at the high-end of the market and become a building block for monster multi-processing machines – when a single chip implementation arrives – and embedded systems, but will gradually replace the R3000 at the low end. Likely to fall into the 40 MIPS to 50 MIPS performance range, it is positioned just above Sun Microsystems’ Sparc chip, but will see action in low-end mass-market machines, he says. Although Sun has a 12-month lead over MIPS at the low end, according to Mashey, MIPS looks to be gearing up for a concerted assault at both the high and low end with its new parts, plus those re-worked versions of the older R3000 from the likes of Integrated Device Technology and Performance Semiconductor, which will be hitting the market soon. Both the R6000 and R4000 – indeed all subsequent MIPS parts – will incorporate the switch implemented in the R3000A, which enables applications to run on machines configured in either big-endian or little-endian byte order without the need for re-compilation. Silicon Graphics, Groupe Bull, Control Data and others have all contributed – informally – to the design of the MIPS processors: Silicon Graphics has concentrated on multi-processing features while Bull has been working on ensuring adherence to X/Open’s Portability Guide standards.
Version of OS/2
Some 70% of MIPS’ business now comes from systems, the other 30% is derived from its bevy of licensing deals, and there are reckoned to be around 600 systems installed in the UK, according to MIPS UK’s Steve Bailey. Mashey – a founder member of the Systems Performance Evaluation Council – says that SPEC’s benchmark tests will be formally separated into into integer and floating-point performance ratings following the demands of member companies. The multi-processing and input-output test suites the Council is working on will be available during the second quarter of next year, although most SPEC companies have already put systems through their paces in these tests, he says. MIPS is keeping the industry guessing about Microsoft Corp’s much-rumoured plan to do a version of OS/2 for its processor or whether Compaq Computer Corp, or indeed any of the other players with undeclared RISC intentions like Tandy Corp and Ing C Olivetti & Co SpA will sign up for its technology. Microsoft would likely be interested in doing an OS/2 version if MIPS – or anyone else – can put together a system that will compete with Intel 80386 and 80486 systems in price. – William Fellows
MIPS camp squares up to Sparc with new R3000 implementations
Following the launch of LSI Logic Corp’s single-chip implementation of MIPS Computer Systems’ R3000 RISC processor las
t month, other players are now lining up behind the R Series with products that are likely to drive the processor down into the low-cost, mass-market end of the RISC business, which Sun Microsystems’ Sparc has been having much to itself recently. Backing MIPS Computers’ John Mashey’s claim that the company is around a year behind Sun at the low-end of the market, these new arrivals could spawn a rash of low-cost MIPS-based systems and embedded applications over the next year or so, similar to the gaggle of Sparc-box builders that have entered the fray over the last few months.
Performance Semiconductor readies highly-integrated version of the R3000
A single-chip implementation of the R3000 combining a CPU, floating-point unit and cache memory in one module is expected to be revealed by Sunnyvale, California-based Performance Semiconductor Corp early next year. To be offered in 25MHz, 35MHz and 40MHz versions, the part will go from $600 to $1,000 for 1,000-up quantities. Performance claims that its PIMM – Performance Integrated Multichip Module – puts the MIPS architecture ahead of the integration and clock-cycle advances made by the Sparc-architecture camp.
Integrated Device offers tool kit for designing embedded R-series systems
Integrated Device Technology Inc, based in Santa Clara, California, has announced a RISC-based tool kit for designing embedded systems based on MIPS’ R3000 part. The Real8 laser printer developer’s toolkit includes an IDT7RS388 processor board which uses a 25MHz R3001. Printer board-makers will be able to speed up Postscript-compatible graphics output by up to 10 times, it is claimed. Resulting printer boards could be out early next year for around $300, the tool kit ships in February for $3,000. Integrated Device is also offering a board-level MIPS R system, the R3501/52, with on-chip caches, prices for which fall as low as $30 in large quantities.
