Paris, France-based Matra MHS SA is developing a family of Sparc V8-based 32-bit microcontrollers in 0.6 micron CMOS at from 50MHz to 70MHz for embedded applications. It calls them Sparclets and plans to target communications systems markets with a general purpose architecture combining RISC, signal processors and on-chip peripherals. Matra redesigned the Sparc pipeline for Sparclet, has had silicon since October and will ship the first products in the third quarter. The 50MHz 90C701 integrates timers, Universal Asynchronous Receiver-Transmitters and a high speed memory interface. RISC core modifications provide signal processor support. Target markets are digital cellular base stations, Integrated Services Digital Network terminals and the general facsimile modem, video-on-demand, digital cellular communication systems and digital television markets. Matra says it already has a Sparclet derivative under development for a car manufacturer. Matra is looking for third party compilers, and DSPlib, emulator, debugger and real time operating system support from independent software vendors. A detailed announcement is expected in the second quarter, but it has already signed Paris neighbour Chorus Systemes SA to provide its new Chorus microkernel on the 90C701 by the end of the year. It is seeking two fabs and plans a technology package release in the third quarter. Matra will move to an 0.5 micron process next year and plans a 300 MIPS 100MHz Sparclet II for 1997 release. Sparclet uses a non-superscalar parallel process architecture and borrows out-of-order techniques. Matra estimates Sparclet derivatives should take 24 months to build. Matra MHS is up against the likes of Fujitsu Ltd’s Sparclite and embedded PowerPC.
