The two companies will present the Interlaken protocol as an open specification with no significant obstacles to adoption by other silicon vendors.
The idea is to enable a third-party market, according to Jim McKeon, product manager at Sunnyvale, California-based Cortina. He said his company wants to compete on the features and functions in our chip rather than on the interface, which we regard as an enabling technology.
There are no plans to engage in any formal standardization process with Interlaken, but McKeon cited precedents, such as when Cisco opened up its serial GMII (SGMII) technology for connections to copper PHY, which resulted in it becoming a de facto standard by virtue of the Cisco’s clout.
Clearly Cisco wants the same thing to happen with Interlaken, as this would foment the development of a range of silicon suppliers from which it could choose, rather than be tied to proprietary approaches such as Broadcom’s HiGig stacking protocol, which enables chip-to-chip comms at up to100Gbps, but only on the chipmaker’s own silicon.
Interlaken builds on both the existing interconnects for 10Gb chip-to-chip communications, McKeon explained.
We used SPI 4.2 at the logical layer, because it has wide acceptance in the market for its ability to carve the bandwidth into virtual channels and manage flows independently, he said. For the physical/electronics layer, meanwhile, we opted for a SerDes, which is the basis for the XAUI interconnect.
SPI 4.2’s physical layer is a parallel bus with a clock, which is extremely difficult to manage at the very high speeds Interlaken is targeting.
The reason the two companies could not base all of Interlaken on XAUI, meanwhile, was that it is designed in such a way that it cannot be extended beyond four SerDes lanes in each direction. We wanted an interconnect that was flexible in the number of SerDes lanes, McKeon said.
At issue here is interconnect technology for chip-to-chip comms within networking devices rather than I/O technology, Cisco having opted for InfiniBand for the latter. Interlaken will nonetheless be relevant, within Cisco network devices in the data center as well as in storage and on wide-area links. Basically it’s for anywhere you require high bandwidths, said McKeon.
This is all about improving board real estate, said Neil Walker, head of product marketing at Cisco in EMEA. Today SPI 4.2 requires 80 pins to do 10Gbps in each direction, and would need many more for higher speeds, he added. With Interlaken you’ll use eight pins for the same functionality.
