Chartered Semiconductor Manufacturing has introduced its new 65-nanometer (nm) RF platform for developers of single-chip RF products.
The new offering, jointly developed with IBM, is based on the company’s 65nm low-power process (65nm LPe) and includes an IBM RF physical design kit (PDK). The RF Platform comes with RF design enablement from analog IP suppliers and the Wireless SoC Platform Alliance (WISPA) consortium.
The kit reportedly reduces design time and ensures ‘first-time-right silicon’ for full-featured SoCs with integrated RF. The PDK enables a methodology, based on a parameterised cell (p-cell) design approach, which allows designers to tune RF components.
The PDK consists of a palette of transistors and passives, including high fT RF transistors, vertical native (VNCAPs) and MIM capacitors, tuning range MOS varactors, Q-factor shielded inductor, precision poly resistors, and RF ESD devices. These device offerings are said to be complemented by RF-centric p-cells – an inductor synthesis kit, EM simulators setup files support and substrate noise analysis kit.
In addition, a range of IP support for RF applications is available for the 65nm RF platform. This includes silicon tested RF subsystems for WiFi, WiMax, and GPS; a host of industry standard interfaces (mDDR/DDR/DDR2, USB 2.0, PCI express, SATA II, and LVDS); and functional analog /mixed signal subsystems (Analog Front End, Audio CODEC, Video ADC/DAC, PLL/DLL, and baseband DAC/ADC).
Further, the company stated that, its enhanced 65nm LPe is supported by an ecosystem of EDA tools and IP blocks, including a broad offering of standard cell and IO libraries from suppliers.
