For the first time, power-saving technology that reduces leakage and battery consumption on the one hand and cuts heat dissipation on the other has been successfully validated in silicon, using the latest 90-nanometer fabrication process, said Himanshu Singh, Executive Director (India/SAARC) of Cadence Design Systems.
The power-efficient design was realised on the industry-standard ARM 1136JF-S chip that forms the heart of many mobile phones and portable wireless devices. The team said they have succeeded in reducing the operating voltage for many sub-circuits from one volt to 0.8 volt.
While Cadence contributed the necessary suite of design tools, UK-based ARM Holdings and US associate company, Artisan Components provided the standard memory libraries and the testing muscle; Applied Materials contributed the 90 nm production facilities and the Taiwan’s TSMC provided the actual silicon foundry facilities.
There was no way any single company could have achieved this, Singh said. This project exemplifies the power of strategic collaboration to significantly differentiate our respective technology offerings.
The development was a result of Silicon Design Chain Initiative that was established by the five companies. The initiative aims to provide proven design flows to solve the most challenging nanometer design issues. Drawing on each company’s domain of expertise, the Silicon Design Chain claims to have correlated models, design and analysis tools, and IP to silicon results, providing customers with a proven path from design to volume production.
The team added that Silicon Design Chain will continue to work on important low-power design solutions will provide process and inspection technologies needed to enable similar advanced chip designs.
