To better compete for real estate in the embedded systems CPU market, MIPS Technologies Inc has consolidated its RISC instruction set architecture into two flavors: MIPS32 and MIPS64. Although most of the established embedded systems vendors have already made their choice of architecture, the demand for new kinds of DSPs, for multimedia processing and the ability to re-use IP and system on a chip integration, mean that new market opportunities are emerging thick and fast. MIPS wouldn’t say how much incremental business having the two product streams is expected to bring, nor how much a license to each will cost, but it has already signed Alchemy Microprocessor Design Group to MIPS32. The company says that maintaining the two streams will allow it to bring new enhancements to market quicker and should provide a more streamlined architecture.
The same developer framework will enable ISVs, tool developers and system suppliers to target both environments. The two streams replace the MIPS architecture I through V designs. MIPS32 includes the MIPS I and II architectures but also the most popular 64-bit features from the III, IV and V designs, which include the R4000 and R5000 CPUs. Making conditional move and prefetch instructions available for the first time in its 32-bit architecture means that developers can for the first time target multimedia and streaming video applications using MIPS. MIPS has also added standardized versions of multiply and add instructions for DSP developers. Until now they have been licensee-specific extensions.
MIPS64 includes all of the latest 64-bit MIPS V architecture together with support for 64-bit floating point co-processors and data caches as well as a 32-bit mode. MIPS32 is available as the 4Kc and 4Kp cores, previously known as Jade and Jade lite. The difference between the low power designs is size; the smaller 4Kp has a generic multiply divide unit. The 4Kc has a faster unit. Texas Instruments and IDT are among the first Jade licensees. The entry-level MIPS64 20K, code-named Opal is due later this year. The high-end, 1,000 MIPS 20Kc will be delivered first as a standalone CPU around year-end, and will be followed by a core.
