By Stephen Phillips

IBM Corp has unveiled a free data bus architecture with openly published specifications it is touting as the de facto industry standard for system-on-a-chip (SOC) designers, and Intellectual Property (IP) and software tool developers.

CoreConnect, launched earlier this week, is compliant with Virtual Socket Interface Alliance (VSIA) guidelines, and is being offered by IBM at no licensing or royalty cost. SOCs integrate microprocessor, digital signal processing, memory and peripheral interfaces on a single sliver of silicon for better performance and cheaper when compared to chipsets of separate components. They are increasingly being used in such devices as mobile phones, DVD players, digital cameras and video cameras, as well as in PCs. Research last year estimated that by 2005, 50% of the integrated circuit market will be driven by demand for SOC products (CI No 3,398).

According to IBM, an industry-standard bus architecture would enable chip manufacturers to mix and match a range of IP modules or cores developed by chip designers, speeding SOC development time and boosting functionality. At the moment different bus architectures used by chip designers make it difficult for manufacturers to assemble IP modules from diverse suppliers. IBM claims CoreConnect, used with a series of pre-configured, pre-tested base model chips it calls superstructures, will cut advanced SOC development cost and time by up to 50%.

Superstructures are chips designed for particular applications with many of the features built in. Where additional functions are needed, superstructures can be easily customized by reusing IP modules rather than having to create a new chip from scratch. The first such superstructure, the PowerPC 405GP, combining a PowerPC microprocessor (clocked at up to 266MHz) with a number of complimentary features on a single chip, was launched alongside CoreConnect on Monday.

IBM has signed up a users group of IP and services providers to support the effort, including computer aided design firms Mentor Graphics Corp and Cadence Design Systems Inc, to develop products based on the CoreConnect bus standard. With no standards currently in this area, IBM says it hopes CoreConnect will be adopted as a default standard. CoreConnect has been the foundation for more than 20 proprietary IBM chip designs during the last two years using IP modules from its own Blue Logic core library.