Synopsys has revealed that CSR has deployed Synopsys’ Galaxy Implementation Platform for the design of its 40nm system-on-chips (SoCs).
CSR has adopted the Galaxy platform for 40nm, high-end Coach14 digital camera chip, and expects it will deliver enhanced hierarchical SoC design flow.
CSR vice president of global chip design Babak Bastani said by using the silicon-proven Galaxy Platform, CSR would be able to predictably tape out differentiated designs that deliver superior performance with low power consumption, which is critical to CSR’s success in these mobile computing markets.
CSR SoC has millions of instances and intellectual property blocks, including Synopsys’ DesignWare USB 2.0 and DDR IP.
CSR noted it was able to deploy a hierarchical flow from synthesis to place-and-route to signoff and achieve on-time tapeout while meeting all of its design specifications.
The Galaxy platform features a Design Compiler Graphical with IC Compiler that provides better RTL-to-physical convergence from initial design exploration through concurrent multi-corner/multi-mode (MCMM) optimisation, and closure for timing, power, testability and area.
It will offer IC Compiler Zroute technology that allows concurrent design-for-manufacturability (DFM) routing for enhanced process technologies.
The platform also comes with In-Design physical verification through IC Validator, IC Compiler which enables fast multicore, lithography-aware routing and delivers full compliance with complex DRC rules required for advanced silicon nodes.
Its PrimeTime HyperScale technology speeds block-level timing closure in the context of the top-level design, accelerating signoff of complex, hierarchical designs.
