This process for flattening the topography during silicon integrated circuit fabrication can provide improvements in cost of ownership, planarization quality, ease of use, process reliability, and cleanliness in comparison to chemical mechanical polishing (CMP) – the current industry norm.
Brewer’s agreement with Agere Systems, formerly the Microelectronics Group of Lucent Technologies is based on development work done at Bell Labs, Lucent’s research and development arm.
As more functionality is added to integrated circuits, the size of individual chip components such as transistors and interconnections is shrinking while the number of component layers is increasing. These two industry trends are at odds with each other, because increasing the number of layers increases the topography, which in-turn limits the lithographic pattern resolution for device geometries. Contact planarization provides a way of removing this topography over a whole wafer as well as over the individual devices on it. This advanced planarization technology is expected to reduce the cost of ownership of planarization steps in manufacturing and improve their quality as well.
