When the ASCI Purple deal was announced a few weeks ago, it was unclear exactly how the top-end Armada machines would be configured. IBM was expected to deliver simultaneous multithreading (SMT) support on the Power5 processors, which presents the operating system in the machine with a virtual two processors for each actual processor core in the server and can increase server throughput by 20% to 30%, depending on the applications. IBM has been saying since the Power4-based Regatta machines were announced at the end of 2001 that it would eventually deliver 64-way machines with up to 512GB of main memory. What wasn’t clear is whether or not IBM was counting SMT running on a 32-way (16 dual core chips) as a 64-way. In a loose sense it is a 64-way machine, but technically, such a machine is not really a 64-way.
As it turns out, the top-end Armada machines will indeed be true 64-way machines, with 32 dual-core Power5 or Power5+ processors in a single system image. The SMT support will allow the machine to present up to 128 virtual processor images to either IBM’s AIX or the open source Linux operating systems that will run on this box. Sources familiar with IBM’s plans also say that IBM has, with the Power5 chip, created a means whereby it can rapidly switch from SMT to non-SMT mode, depending on how applications react to this technology. For databases in particular, IBM expects SMT to provide significant performance benefits, these sources say, but we have not been able to get any hard figures on exactly what kind of boost to expect.
The Armada machines look like they are going to come in two flavors: one that scales from two to eight processors and one that scales from eight to 64 processors. As was the case with the Power4 and Power4+ Regatta servers, the Power5 chip will include two processor cores and an integrated switch for linking four dual-core processors into a single eight-way machine. This eight-way Power5 unit of processing power will support 64GB of main memory, up from 32GB with the Power4 machines. With the Power5-Armada generation of machine, IBM is bringing the memory controller onto the chip and will integrate L3 cache memories onto the multichip module that the Power4 and Power5 chips get packaged in for big SMP boxes. Power4 machines have external L3 caches and only a memory look up table (rather than the full controller) is on the chip. The Power5 chips are also expected to have larger integrated L2 caches than the Power4 and Power4+ generations, which top out at 1.44MB per chip and 1.5MB per chip, respectively. IBM is expected to make enhancements in the electronics in the Power5 chip to accelerate floating point operations as well as for common database and networking tasks like running the TCP/IP protocol.
The Power5 chip will be implemented in a 0.13 micron process, just like the Power4+ chip that was just announced in the pSeries 650 midrange server a month ago. Those Power4+ chips are now offered at 1.2GHz and 1.45GHz, and are expected to reach 1.7GHz or maybe even 1.8GHz during 2003 in the Regatta boxes. Further refinements in the 0.13 micron process in 2003 and early 2004 should allow IBM to deliver initial Power5 chips running at 1.4GHz or 1.5GHz, with top-end speeds hitting 2GHz or maybe even higher. A 64-way Armada machine without SMT activated could hit 1 million transactions per minute on the TPC-C online transaction processing benchmark test, and with SMT turned on, all the bigger caches and tighter integration, could do well above that. The key thing here is could. It’s a long way to 2004. But IBM seems keen on delivering Power-based machines that will be able to keep pace with the biggest Unix boxes that Hewlett Packard Co, Sun Microsystems, and Fujitsu Siemens can get out the door. timpm@computerwire.com
Source: Computerwire
